参数资料
| 型号： | MC14LC5540DW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC CODEC ADPCM 28-SOIC W |
| 标准包装： | 26 |
| 类型： | ADPCM 编解码器/滤波器 |
| 数据接口： | PCM 音频接口 |
| 分辨率（位）： | 13 b |
| ADC / DAC 数量： | 1 / 1 |
| 三角积分调变： | 无 |
| 电压 - 电源，数字： | 4.5V ~ 5.5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 管件 |
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MC145484
MOTOROLA
17
DIGITAL SWITCHING CHARACTERISTICS FOR IDL MODE
(VDD = 5.0 V ± 10%, TA = – 40 to + 85°C, CL = 150 pF, See Figure 5 and Note 1)
Ref.
No.
Characteristics
Min
Max
Unit
31
Time Between Successive IDL Syncs
Note 2
32
Hold Time of IDL SYNC After Falling Edge of IDL CLK
20
—
ns
33
Setup Time of IDL SYNC Before Falling Edge IDL CLK
60
—
ns
34
IDL Clock Frequency
256
4096
kHz
35
IDL Clock Pulse Width High
50
—
ns
36
IDL Clock Pulse Width Low
50
—
ns
37
Data Valid on IDL RX Before Falling Edge of IDL CLK
20
—
ns
38
Data Valid on IDL RX After Falling Edge of IDL CLK
75
—
ns
39
Falling Edge of IDL CLK to High–Z on IDL TX
10
50
ns
40
Rising Edge of IDL CLK to Low–Z and Data Valid on IDL TX
10
60
ns
41
Rising Edge of IDL CLK to Data Valid on IDL TX
—
50
ns
NOTES:
1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.
2. In IDL mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words
are accessed during the B2 channel as shown in Figure 5. IDL accesses must occur at a rate of 8 kHz (125
s interval).
CH1
MSB
IDL TX
(DT)
LSB
ST3
ST2
ST1
CH3
CH2
CH1
MSB
LSB
ST3
ST2
ST1
CH3
CH2
CH1
MSB
LSB
ST3
ST2
ST1
CH3
CH2
CH1
MSB
LSB
ST3
ST2
ST1
CH3
IDL RX
(DR)
IDL CLOCK
(BCLKT)
IDLE SYNC
(FST)
2
1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
32
33
32
34
35
40
41
36
39
40
41
39
37
38
CH2
Figure 5. IDL Interface Timing
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