参数资料
| 型号： | MC14LC5540DW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 6/28页 |
| 文件大小： | 0K |
| 描述： | IC CODEC ADPCM 28-SOIC W |
| 标准包装： | 26 |
| 类型： | ADPCM 编解码器/滤波器 |
| 数据接口： | PCM 音频接口 |
| 分辨率（位）： | 13 b |
| ADC / DAC 数量： | 1 / 1 |
| 三角积分调变： | 无 |
| 电压 - 电源，数字： | 4.5V ~ 5.5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 管件 |
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MC145484
MOTOROLA
14
DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC
(VDD = + 5 V ± 10%, VSS = 0 V, All Digital Signals Referenced to VSS, TA = – 40 to + 85°C, CL = 150 pF, Unless Otherwise Noted)
Ref.
No.
Characteristics
Min
Typ
Max
Unit
1
Master Clock Frequency for MCLK
—
256
512
1536
1544
2048
2560
4096
—
kHz
1
MCLK Duty Cycle for 256 kHz Operation
45
—
55
%
2
Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater)
50
—
ns
3
Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater)
50
—
ns
4
Rise Time for All Digital Signals
—
50
ns
5
Fall Time for All Digital Signals
—
50
ns
6
Setup Time from MCLK Low to FST High
50
—
ns
7
Setup Time from FST High to MCLK Low
50
—
ns
8
Bit Clock Data Rate for BCLKT or BCLKR
64
—
4096
kHz
9
Minimum Pulse Width High for BCLKT or BCLKR
50
—
ns
10
Minimum Pulse Width Low for BCLKT or BCLKR
50
—
ns
11
Hold Time from BCLKT (BCLKR) Low to FST (FSR) High
20
—
ns
12
Setup Time for FST (FSR) High to BCLKT (BCLKR) Low
80
—
ns
13
Setup Time from DR Valid to BCLKR Low
0
—
ns
14
Hold Time from BCLKR Low to DR Invalid
50
—
ns
LONG FRAME SPECIFIC TIMING
15
Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low
50
—
ns
16
Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data
—
60
ns
17
Delay Time from BCLKT High to DT for Valid Chord and Step Bit Data
—
60
ns
18
Delay Time from the Later of the 8th BCLKT Falling Edge, or the Falling Edge
of FST to DT Output High Impedance
10
—
60
ns
19
Minimum Pulse Width Low for FST or FSR
50
—
ns
SHORT FRAME SPECIFIC TIMING
20
Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low
50
—
ns
21
Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low
50
—
ns
22
Delay Time from BCLKT High to DT Data Valid
10
—
60
ns
23
Delay Time from the 8th BCLKT Low to DT Output High Impedance
10
—
60
ns
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