参数资料
型号: MC33911BAC
厂商: Freescale Semiconductor
文件页数: 79/92页
文件大小: 0K
描述: IC SYSTEM BASIS CHIP 32LQFP
标准包装: 250
应用: 系统基础芯片
电流 - 电源: 4.5mA
电源电压: 5.5 V ~ 27 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 托盘
MC33911BAC / MC34911BAC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
33911 SPI INTERFACE AND CONFIGURATION
The serial peripheral interface creates the communication
link between a microcontroller (master) and the 33911.
The interface consists of four pins (see Figure 43 ):
? CS — Chip Select
? MOSI — Master-Out Slave-In
? MISO — Master-In Slave-Out
? SCLK— Serial Clock
A complete data transfer via the SPI consists of 1 byte. The
master sends 4 bits of address (A3:A0) + 4 bits of control
information (C3:C0) and the slave replies with 4 system
status bits (VMS,LINS,HSS,LSS) + 4 bits of status
information (S3:S0).
CS
Register Write Data
MOSI
A3
A2
A1
A0
C3
C2
C1
C0
Register Read Data
MISO
VMS LINS HSS
LSS
S3
S2
S1
S0
SCLK
Read Data Latch
Rising Edge of SCLK
Change MISO/MISO Output
Falling Edge of SCLK
Sample MISO/MISO Input
Figure 43. SPI Protocol
Write Data Latch
During the inactive phase of the CS (HIGH), the new data
transfer is prepared.
The falling edge of the CS indicates the start of a new data
transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).
With the rising edge of the SPI clock (SCLK), the data is
moved to MISO/MOSI pins. With the falling edge of the SPI
clock (SCLK), the data is sampled by the receiver.
The data transfer is only valid if exactly 8 sample clock edges
are present during the active (low) phase of CS .
The rising edge of the Chip Select ( CS) indicates the end of
the transfer and latches the write data (MOSI) into the
register. The CS high forces MISO to the high-impedance
state.
Register reset values are described along with the reset
condition. Reset condition is the condition causing the bit to
be set to its reset value. The main reset conditions are:
- Power-On Reset (POR): level at which the logic is reset and
BATFAIL flag sets.
- Reset mode
- Reset done by the RST pin (ext_reset)
33911
Analog Integrated Circuit Device Data ?
79
Freescale Semiconductor
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