参数资料
型号: MC33912BACR2
厂商: Freescale Semiconductor
文件页数: 44/95页
文件大小: 0K
描述: IC SYSTEM BASIS CHIP 32LQFP
标准包装: 2,000
应用: 系统基础芯片
电流 - 电源: 4.5mA
电源电压: 5.5 V ~ 27 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 带卷 (TR)
MC33912G5AC / MC34912G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Timing Control Register - TIMCR
This register allows to configure the watchdog, the cyclic
sense and Forced Wake-up periods. Writing to the Timing
Control Register (TIMCR) will also return the Watchdog
Status Register (WDSR).
This option is only active if one of the high side switches is
enabled when entering in Stop or Sleep mode. Otherwise, a
timed wake-up is performed after the period shown in
Table 25. Cyclic Sense and Force Wake up Interval
Table 23. Timing Control Register - $A
CYSX8 (72)
CYST2
CYST1
CYST0
Interval
C3
C2
C1
C0
X
0
0
0
No cyclic sense (73)
0
0
0
1
20 ms
Write
Reset
Value
Reset
Condition
CS/WD
-
-
WD2
CYST2
0
WD1
CYST1
0
POR
WD0
CYST0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
40 ms
60 ms
80 ms
100 ms
120 ms
140 ms
CS/WD - Cyclic Sense or Watchdog Prescaler Select
This write-only bit selects which prescaler is being written to,
the Cyclic Sense/Forced Wake-up prescaler or the Watchdog
prescaler.
1 = Cyclic Sense/Forced Wake-up Prescaler selected
0 = Watchdog Prescaler select
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
160 ms
320 ms
480 ms
640 ms
800 ms
960 ms
WDx - Watchdog Prescaler
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 24 . This configuration is valid only if
windowing watchdog is active.
1 1 1 1 1120 ms
Notes
72. bit CYSX8 is located in Configuration Register (CFR)
73. No Cyclic Sense and no Force Wake-up available.
Watchdog Status Register - WDSR
Table 24. watchdog Prescaler
WD2 WD1 WD0
Prescaler Divider
This register returns the Watchdog status information and is
also returned when writing to the TIMCR.
0
0
0
1
Table 26. Watchdog Status Register - $A/$B
0
0
1
2
S3
S2
S1
S0
0
0
1
1
0
1
4
6
Read
WDTO
WDERR
WDOFF
WDWO
1
1
1
1
0
0
1
1
0
1
0
1
8
10
12
14
WDTO - Watchdog Timeout
This read-only bit signals the last reset was caused by either
a watchdog timeout or by an attempt to clear the Watchdog
within the window closed.
Any access to this register or the Timing Control Register
CYSTx - Cyclic Sense Period Prescaler Select
This write-only bits selects the interval for the wake-up cyclic
sensing together with the bit CYSX8 in the Configuration
(TIMCR) will clear the WDTO bit.
1 = Last reset caused by watchdog timeout
0 = None
Register (CFR) (see page 45 ).
33912
Analog Integrated Circuit Device Data ?
44
Freescale Semiconductor
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