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| 型号： | MC33912BACR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 89/95页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM BASIS CHIP 32LQFP |
| 标准包装： | 2,000 |
| 应用： | 系统基础芯片 |
| 电流 - 电源： | 4.5mA |
| 电源电压： | 5.5 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 带卷 (TR) |
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MC33912BAC / MC34912BAC
FUNCTIONAL DEVICE OPERATIONS
Interrupt Mask Register - IMR
This register allows masking of some of the interrupt sources.
The respective flags within the Interrupt Source Register
(ISR) will continue to work but will not generate interrupts to
the MCU. The 5.0 V Regulator over-temperature prewarning
interrupt and Under-Voltage (VSUV) interrupts can not be
masked and will always cause an interrupt.
Writing to the IMR will return the ISR.
Table 60. Interrupt Mask Register - $E
C3 C2 C1 C0
LINM - LIN Interrupts Mask
This write-only bit enables/disables interrupts generated in
the LIN block.
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
VMM - Voltage Monitor Interrupt Mask
This write-only bit enables/disables interrupts generated in
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the V SUP over-voltage interrupt.
1 = Interrupts Enabled
Write
Reset
Value
HSM
1
LSM
1
LINM
1
VMM
1
0 = Interrupts Disabled
Interrupt Source Register - ISR
This register allows the MCU to determine the source of the
Reset
Condition
POR
last interrupt or wake-up respectively. A read of the register
acknowledges the interrupt and leads IRQ pin to high, in case
HSM - High Side Interrupt Mask
This write-only bit enables/disables interrupts generated in
the high side block.
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
there are no other pending interrupts. If there are pending
interrupts, IRQ will be driven high for 10 μs and then be
driven low again.
This register is also returned when writing to the Interrupt
Mask Register (IMR).
Table 61. Interrupt Source Register - $E/$F
LSM - Low Side Interrupt Mask
S3
S2
S1
S0
This write-only bit enables/disables interrupts generated in
the low side block.
Read
ISR3
ISR2
ISR1
ISR0
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled
ISRx - Interrupt Source Register
These read-only bits indicate the interrupt source following
In case more than one interrupt is pending, the interrupt
sources are handled sequentially multiplex.
Table 62. Interrupt Sources
Interrupt Source
Priority
ISR3 ISR2 ISR1 ISR0
none maskable
maskable
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
no interrupt
-
-
no interrupt
Lx Wake-up from Stop mode-
HS Interrupt (Over-temperature)
LS Interrupt (Over-temperature)
LIN Interrupt (RXSHORT, TXDOM, LIN OT, LIN
none
highest
OC) or LIN Wake-up
0
1
0
1
Voltage Monitor Interrupt
Voltage Monitor Interrupt
(Low Voltage and VDD over-temperature)
(High Voltage)
0
1
1
0
-
Forced Wake-up
lowest
33912
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
89
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