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| 型号： | MC33931VWR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 22/26页 |
| 文件大小： | 0K |
| 描述： | IC H-BRIDGE THROTTLE CTRL 44HSOP |
| 标准包装： | 750 |
| 类型： | 半桥 |
| 输入类型： | 非反相 |
| 输出数： | 2 |
| 导通状态电阻： | 120 毫欧 |
| 电流 - 峰值输出： | 5A |
| 电源电压： | 5 V ~ 28 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-BSSOP（0.433"，11.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 44-HSOP |
| 包装： | 带卷 (TR) |
ADDITIONAL DOCUMENTATION
PACKAGE DIMENSIONS
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM
Introduction
This thermal addendum is provided as a supplement to the MC33931 technical datasheet. The addendum provides thermal
performance information that may be critical in the design and development of system applications. All electrical, application, and
packaging information is provided in the datasheet.
Package and Thermal Considerations
The MC33931 is offered in a 32-pin SOICW-EP and a 44-pin HSOP single die package. There is a single heat source (P), a
single junction temperature (T J ), and thermal resistance (R θ JA ). This thermal addendum is specific to the 32-pin SOICW-EP
package.
T J
=
R θ JA
.
P
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to, and will not predict the performance of a package in an application-specific environment.
Stated values were obtained by measurement and simulation according to the standards listed below.
Table 6. Table of Thermal Resistance Data
Rating
Value
Unit
Notes
Junction to Ambient
Single Layer board (1s)
R θ JA
92
°C/W
Natural Convection
Junction to Ambient
Four layer board (2s2p)
R θ JA
26.6
°C/W
Natural Convection
Junction to Board
Junction to Case (bottom / flag)
Junction to Case (top)
R θ JB
R θ JC (bottom)
R θ JC (top)
7.0
0.62
23.3
°C/W
°C/W
°C/W
Junction to Package Top
Natural Convection
Ψ JT
2.7
°C/W
Notes
32. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
33. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
34. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
35. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
36. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
37. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
38. Thermal resistance between the die and the case bottom / flag surface (simulated) (flag bottom side fixed to ambient temperature).
33931
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
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