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| 型号： | MC33931VWR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 8/26页 |
| 文件大小： | 0K |
| 描述： | IC H-BRIDGE THROTTLE CTRL 44HSOP |
| 标准包装： | 750 |
| 类型： | 半桥 |
| 输入类型： | 非反相 |
| 输出数： | 2 |
| 导通状态电阻： | 120 毫欧 |
| 电流 - 峰值输出： | 5A |
| 电源电压： | 5 V ~ 28 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-BSSOP（0.433"，11.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 44-HSOP |
| 包装： | 带卷 (TR) |
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.0 V ≤ V PWR ≤ 28 V, - 40 ° C ≤ T A ≤ 125 ° C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency (20)
f PWM
–
–
11
kHz
Maximum Switching Frequency During Current Limit Regulation
f MAX
–
–
20
kHz
Output ON Delay
t DON
μ s
V PWR = 14 V
Output OFF Delay (22)
V PWR = 14 V
t DOFF
–
–
–
–
18
12
μ s
I LIM Output Constant-OFF Time (23) (25)
I LIM Blanking Time (24) (25)
Disable Delay Time (26)
Output Rise and Fall Time (27)
Power-ON Delay Time (29)
Output MOSFET Body Diode Reverse Recovery Time (29)
Charge Pump Operating Frequency (29)
t A
t B
t DDISABLE
t F , t R
t FAULT
t POD
t RR
f CP
15
12
–
1.5
–
–
75
–
20.5
16.5
–
3.0
–
1.0
100
7.0
32
27
8.0
8.0
8.0
5.0
150
–
μ s
μ s
μ s
μ s
μ s
ms
ns
MHz
Notes
20. The maximum PWM frequency should be limited to frequencies < 11 kHz in order to allow the internal high side driver circuitry time to
fully enhance the high side MOSFETs.
21. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s
inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM
frequency during current limit.
22.
* Output Delay is the time duration from 1.5 V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5 V on the input signal to the 80% point of
the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5 V on the input signal to the 20% point of the
23. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
24. The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time
to act.
25. Parameter is Guaranteed By Characterization.
26.
27. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with V PWR = 14 V,
28.
29.
Load currents ramping up to the current regulation threshold become limited at the I LIM value (see Figure 7 ). The short-circuit currents
possess a di/dt that ramps up to the I SCH or I SCL threshold during the I LIM blanking time, registering as a short-circuit event detection and
causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode
may cause junction temperatures to rise. Junction temperatures above ~160 ° C will cause the output current limit threshold to “fold back”,
or decrease, until ~175 ° C is reached, after which the T LIM thermal latch-OFF will occur. Permissible operation within this fold back region
is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9 ).
Parameter is Guaranteed By Design.
33931
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
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