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参数资料
| 型号： | MC33931VWR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 3/26页 |
| 文件大小： | 0K |
| 描述： | IC H-BRIDGE THROTTLE CTRL 44HSOP |
| 标准包装： | 750 |
| 类型： | 半桥 |
| 输入类型： | 非反相 |
| 输出数： | 2 |
| 导通状态电阻： | 120 毫欧 |
| 电流 - 峰值输出： | 5A |
| 电源电压： | 5 V ~ 28 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-BSSOP（0.433"，11.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 44-HSOP |
| 包装： | 带卷 (TR) |
PIN CONNECTIONS
PIN CONNECTIONS
AGND
D1
FB
EN/D2
VPWR
VPWR
VPWR
OUT1
OUT1
OUT1
PGND
PGND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Tab
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SF
IN1
IN2
CCP
VPWR
VPWR
OUT2
OUT2
OUT2
PGND
PGND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
AGND
D1
FB
N/C
EN/D2
N/C
VPWR
VPWR
N/C
OUT1
OUT1
N/C
N/C
N/C
PGND
PGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SF
IN1
N/C
IN2
CCP
N/C
VPWR
VPWR
N/C
OUT2
OUT2
N/C
N/C
N/C
PGND
PGND
Tab
44 HSOP
Transparent Top View
32 SOICW-EP
Transparent Top View
Figure 3. 33931 Pin Connections
Table 1. 33931 Pin Definitions
A functional description of each pin can be found in the Functional Description section beginning on page 11 .
Pin
HSOP
(VW)
1
Pin
SOICW-EP
(EK)
2
Pin
Name
D1
Pin
Function
Logic Input
Formal Name
Disable Input 1
(Active High)
Definition
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated.
Schmitt trigger input with ~80 μ A source so default condition =
disabled.
2
3
FB
Analog
Feedback
The load current feedback output provides ground referenced
Output
0.24% of the high side output current. (Tie to GND through a
resistor if not used.)
3
5
EN/D2
Logic Input
Enable Input
When EN/D2 is logic HIGH the H-bridge is operational. When EN/
D2 is logic LOW, the H-bridge outputs are tri-stated and placed in
Sleep mode. (logic input with ~ 80 μ A sink so default condition =
Sleep mode.)
4-6, 40, 39
7, 8, 25, 26
VPWR
Power Input
Positive Power
These pins must be connected together physically as close as
Supply
possible and directly soldered down to a wide, thick, low
resistance supply plane on the PCB.
7-9
10, 11
OUT1
Power
H-bridge Output 1
Source of HS1 and drain of LS1.
Output
10, 11, 34,
15-18
PGND
Power
Power Ground
High-current power ground pins must be connected together
35
Ground
physically as close as possible and directly soldered down to a
wide, thick, low resistance ground plane on the PCB.
36-38
22, 23
OUT2
Power
H-bridge Output 2
Source of HS2 and drain of LS2.
Output
33931
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
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