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参数资料
| 型号： | MC35XS3500PNA |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 17/45页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HIGHSIDE 24PQFN |
| 标准包装： | 168 |
| 类型： | 高端开关 |
| 输出数： | 5 |
| Rds（开）： | * |
| 内部开关： | 是 |
| 电流限制： | 9A |
| 输入电压： | 7 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 托盘 |
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ? V CC ? 5.5 V, 7.0 V ? V BAT ? 20 V, -40 ?? C ? T A ? 125 ?? C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T A = 25 ?? C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
f SPI
–
–
3.0
MHz
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
t CS
–
–
1.0
us
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (48)
Required High State Duration of SCLK (Required Setup Time) (48)
Required Low State Duration of SCLK (Required Setup Time) (48)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (48)
SI to Falling Edge of SCLK (Required Setup Time) (49)
Falling Edge of SCLK to SI (Required Setup Time) (49)
t LEAD
t WSCLKH
t WSCLKl
t LAG
t SI SU
t SI HOLD
–
–
–
–
–
–
–
–
–
50
25
25
500
167
167
167
83
83
ns
ns
ns
ns
ns
ns
SO Rise Time
t RSO
ns
C L = 80 pF
SO Fall Time
C L = 80 pF
t FSO
–
–
25
25
50
50
ns
SI, CS, SCLK, Incoming Signal Rise Time (50)
SI, CS, SCLK, Incoming Signal Fall Time (50)
Time from Falling Edge of CS to SO Low-impedance (51)
Time from Rising Edge of CS to SO High-impedance (52)
t RSI
t FSI
t SO(EN)
t SO(DIS)
–
–
–
–
–
–
–
65
50
50
145
145
ns
ns
ns
ns
Notes
48.
49.
50.
51.
52.
Maximum setup time required for th e 35XS3500 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS , and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 k ?? on pull-up on CS .
Time required for output status data to be terminated at SO. 1.0 k ?? on pull-up on CS .
Time required to obtain valid data out from SO following the rise of SCLK.
35XS3500
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
17
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