- 您现在的位置：买卖IC网 > PDF目录16879 > MC35XS3500PNA (Freescale Semiconductor)IC SWITCH HIGHSIDE 24PQFN PDF资料下载
参数资料
| 型号： | MC35XS3500PNA |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 21/45页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HIGHSIDE 24PQFN |
| 标准包装： | 168 |
| 类型： | 高端开关 |
| 输出数： | 5 |
| Rds（开）： | * |
| 内部开关： | 是 |
| 电流限制： | 9A |
| 输入电压： | 7 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
Limp Home (LIMP)
The Limp Home mode of the component can be activated
by this digital input port. The signal is “high active”, meaning
the Fail mode can be activated by a logic high signal at the
input.
Ignition Input (IGN)
The Ignition input wakes the device. It also controls the
Fail Home mode activation. The signal is “high active”,
meaning the component is active in case of a logic high at the
input.
Flasher Input (FLASHER)
The Flasher input wakes the device. It also controls the
Fail mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
Reset Input (RST)
This input wakes the device when the RST pin is at
logic [1]. It is also used to initialize the device configuration
and the SPI fault registers when the signal is low. All SI/SO
registers described in Table 9 and Table are reset. The fault
management is not affected by RST (see Figure 2 ).
Current Sense Output (CSNS)
The current sense output pin is an analog current output or
a voltage proportional to the temperature on the GND flag.
The routing to the common resistor is SPI programmable.
This current sense monitoring may be synchronized in
case of the OUT6 is not used. So, the current sense
monitoring can be synchronized with a rising edge on the
FETOUT pin (t CSNS(SYNC) ) if CSNS sync SPI bit is set to logic
[1]. Connection of the FETOUT pin to a MCU input pin allows
the MCU to sample the CSNS pin during a valid time-slot.
Since this falling edge is generated at the end of this timeslot,
upon a switch-off command, this feature may be used to
implement maximum current control.
Charge Pump (CP)
An external capacitor is connected between this pin and
FETOUT Output (FETOUT)
This output pin is used to control an external MOSFET
(OUT6).
The high level of the FETOUT Output is VCC if V BAT and
V CC are available in case of FETOUT is controlled ON.
FETOUT is not protected in case of a short-circuit or
under-voltage on V BAT .
In case of a reverse battery, OUT6 is OFF.
FETIN Input (FETIN)
This input pin gives the current recopy of the external
MOSFET. It can be routed on the CSNS output by a SPI
command.
SPI Protocol Description
The SPI interface has a full-duplex, three-wire
synchronous data transfer with four I /O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (CS).
The SI/SO pins of the 35XS3500 device follow a first-in,
first-out (D15 to D0) protocol, with both input and output
words transferring the most significant bit (MSB) first. All
inputs are compatible with 5.0 V CMOS logic levels supplied
by V CC .
The SPI lines perform the following functions:
Serial Clock (SCLK)
The SCLK pin clocks the internal shift registers of the
35XS3500 device. The SI pin accepts data into the input shift
register on the falling edge of the SCLK signal, while the SO
pin shifts data information out of the SO line driver on the
rising edge of the SCLK signal. It is important that the SCLK
pin be in a logic low state whenever CS makes any transition.
For this reason, it is recommended that the SCLK pin be in a
logic [0] whenever the device is not accessed (CS logic [1]
state). SCLK has a passive pull-down, R DWN . When CS is
logic [1], signals at the SCLK and SI pins are ignored and SO
is tri-stated (high-impedance) (see Figure 8 ).
the VBAT pin. It is used as a tank for the internal charge
pump. Its typical value is 100 nF ± 20%, 25 V maximum.
35XS3500
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
21
相关PDF资料 |
PDF描述 |
|---|---|
| GCC25DCMD-S288 | CONN EDGECARD 50POS .100 EXTEND |
| 342A124-4/42-0 | BOOT MOLDED |
| TCMD-17-D-02.00-01 | CABLE ASSEM 2MM 34POS M-M 2" |
| MC10XS3535PNAR2 | IC SWITCH HIGHSIDE 24PQFN |
| EBC31DCSN-S288 | CONN EDGECARD 62POS .100 EXTEND |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC35XS3500PNAR2 | 功能描述:功率驱动器IC 5 OUTPUT ESWITCH RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| MC36089 | 制造商:SPC Multicomp 功能描述:ESD OPEN BIN BOX; ESD Storage Type:Bin; External Depth - Imperial:24.75"; External Depth - Metric:628.65mm; External Height - Imperial:4.5"; External Height - Metric:114.3mm; External Width - Imperial:4.25"; External Depth:24-3/4" ;RoHS Compliant: NA |
| MC36090 | 制造商:SPC Multicomp 功能描述:ESD OPEN BIN BOX; ESD Storage Type:Bin; External Depth - Imperial:24.75"; External Depth - Metric:628.65mm; External Height - Imperial:4.5"; External Height - Metric:114.3mm; External Width - Imperial:2.25"; External Depth:24-3/4" ;RoHS Compliant: NA |
| MC36091 | 制造商:SPC Multicomp 功能描述:ESD OPEN BIN BOX; ESD Storage Type:Bin; External Depth - Imperial:18"; External Depth - Metric:457.2mm; External Height - Imperial:4.5"; External Height - Metric:114.3mm; External Width - Imperial:4"; External Width - Metric:101.6mm ;RoHS Compliant: NA |
| MC36092 | 制造商:SPC Multicomp 功能描述:ESD OPEN BIN BOX; ESD Storage Type:Bin; External Depth - Imperial:18"; External Depth - Metric:457.2mm; External Height - Imperial:4.5"; External Height - Metric:114.3mm; External Width - Imperial:2"; External Width - Metric:50.8mm ;RoHS Compliant: NA |
发布紧急采购，3分钟左右您将得到回复。