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| 型号： | MC38HC705J2 |
| 厂商： | Motorola, Inc. |
| 元件分类： | DC/DC变换器 |
| 英文描述： | RTS Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 3.3V; Power: 2W; Assembly; High Power Density; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| 中文描述： | M68HC05系列系列8位微控制器单元 |
| 文件页数： | 48/78页 |
| 文件大小： | 427K |
| 代理商： | MC38HC705J2 |
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MOTOROLA
5-2
RESETS AND INTERRUPTS
MC68HC705J2
A 4064 tcyc (internal clock cycle) delay after the oscillator becomes active
allows the clock generator to stabilize. If the RESET pin is at a logical zero at
the end of 4064 tcyc, the MCU remains in the reset condition until the signal on
the RESET pin goes to a logical one.
5.1.2 External Reset
A zero applied to the RESET pin for one and one-half tcyc generates an
external reset. A Schmitt trigger senses the logic level at the RESET pin.
5.1.3 Computer Operating Properly (COP) Reset
A timeout of the COP timer generates a COP reset. The COP timer is part of a
software error detection system and must be cleared periodically to start a new
timeout period. (See
7.3 COP Timer
.) To clear the COP timer and prevent a
COP reset, write a zero to bit 0 (COPR) of the COP control register at location
$0FF0 before the COP timer times out. The COP control register is a write-only
register that returns the contents of an EPROM location when read. See Figure
5-1.
COPR —
COP Control Register
$0FF0
Bit 7
—
—
6
—
—
5
—
—
4
—
—
3
—
—
2
—
—
1
—
—
Bit 0
COPR
0
RESET
Figure 5-1. COP Control Register
COPR — COP Reset
COPR is a write-only bit. Periodically writing a zero to COPR prevents the COP
timer from resetting the MCU.
5.1.4 Illegal Address Reset
An opcode fetch from an address that is not in the EPROM (locations $0700–
$0EFF), or the RAM ($0090–$00FF) generates an illegal address reset.
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