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| 型号： | MC38HC705J2 |
| 厂商： | Motorola, Inc. |
| 元件分类： | DC/DC变换器 |
| 英文描述： | RTS Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 3.3V; Power: 2W; Assembly; High Power Density; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| 中文描述： | M68HC05系列系列8位微控制器单元 |
| 文件页数： | 50/78页 |
| 文件大小： | 427K |
| 代理商： | MC38HC705J2 |
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MOTOROLA
5-4
RESETS AND INTERRUPTS
MC68HC705J2
The return from interrupt (RTI) instruction causes the CPU to recover the CPU
registers from the stack as shown in Figure 5-2.
5.2.1 Timer Interrupts
The timer generates two kinds of interrupts:
Timer overflow interrupt
Real-time interrupt
Setting the interrupt mask in the condition code register disables timer
interrupts.
5.2.1.1 Timer Overflow Interrupts
A timer overflow interrupt occurs if the timer overflow flag, TOF, becomes set
while the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE
are in the timer control and status register. See
7.2 Timer Control and
Status Register
.
5.2.1.2 Real-Time Interrupts
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set
while the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in
the timer control and status register. See
7.2 Timer Control and Status
Register
.
5.2.2 External Interrupt
When a falling edge occurs on the IRQ pin, an external interrupt request is
latched. When the CPU completes its current instruction, it tests the external
interrupt latch. If the interrupt latch is set and the interrupt mask in the condition
code register is reset, the CPU then begins the interrupt sequence. The CPU
clears the interrupt latch while it fetches the interrupt vector, so that another
external interrupt request can be latched during the interrupt service routine. As
soon as the interrupt mask is cleared (usually during the return from interrupt),
the CPU can recognize the new interrupt request.
Figure 5-3 shows the sequence of events caused by an interrupt.
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