- 您现在的位置：买卖IC网 > PDF目录132989 > MC56F8013VFAER2 (FREESCALE SEMICONDUCTOR INC) 0-BIT, 8 MHz, OTHER DSP, PQFP32 PDF资料下载
参数资料
| 型号： | MC56F8013VFAER2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封装： | ROHS COMPLIANT, LQFP-32 |
| 文件页数： | 105/125页 |
| 文件大小： | 1702K |
| 代理商： | MC56F8013VFAER2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页当前第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页
56F8013/56F8011 Data Sheet, Rev. 11
80
Freescale Semiconductor
The power modes provide additional means to disable clock domains, configure the voltage regulator, and
configure clock generation to manage power utilization, as shown in Table 6-3. Run, Wait, and Stop
modes provide means of enabling/disabling the peripheral and/or core clocking as a group. Stop disable
controls are provided for selected peripherals in the control register so that these peripheral clocks can
optionally continue to operate in Stop mode and generate interrupts which will return the part from Stop
to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is
possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction.
A 200kHz clock external clock can optionally be used in Standby mode to produce the required Standby
100kHz system bus rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully
disables the part and minimizes its power utilization but is only recoverable via reset.
When the PLL is not selected and the system bus is operating at around 100kHz, the large regulator can
be put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator.
Wait
Core and memory
clocks disabled
Peripheral clocks
enabled
Core executes WAIT instruction to enter this
mode.
Typically used for power-conscious applications.
Possible recoveries from Wait mode to Run
mode are:
1. Any interrupt
2. Executing a Debug mode entry command
during the 56800E core JTAG interface
2. Any reset (POR, external, software, COP)
Stop
Master clock generation in the OCCS
remains operational, but the SIM disables
the generation of system and peripheral
clocks.
Core executes STOP instruction to enter this
mode. Possible recoveries from Stop mode to
Run mode are:
1. Interrupt from Timer channels that have been
configured to operate in Stop mode (TCx_SD)
2. Interrupt for SCI configured to operate in Stop
mode (SCI_SD)
3. Low-voltage interrupt
4. Executing a Debug mode entry command
using the 56800E core JTAG interface
5. Any reset (POR, external, software, COP)
Standby
The OCCS generates the 2X system clock
at a reduced frequency (200kHz). The PLL
and high speed peripheral clocks are
disabled and the high-speed peripheral
option is not available. System and
peripheral clocks operate at 100kHz.
The user configures the OCCS and SIM to select
the relaxation oscillator clock source (PRECS),
shut down the PLL (PLLPD), put the relaxation
oscillator in Standby mode (ROSB), and put the
large regulator in Standby (LRSTDBY). The part
is fully operational, but operating at a minimum
frequency and power configuration. Recovery
requires reversing the sequence used to enter
this mode (allowing for PLL lock time).
Power-Down
Master clock generation in the OCCS is
completely shut down. All system and
peripheral clocks are disabled.
The user configures the OCCS and SIM to enter
Standby mode as shown in the previous
description, followed by powering down the
oscillator (ROPD). The only possible recoveries
from this mode are:
1. External Reset
2. Power-On Reset
Table 6-3 Clock Operation in Power-Down Modes (Continued)
Mode
Core Clocks
Peripheral Clocks
Description
相关PDF资料 |
PDF描述 |
|---|---|
| MCIMX31VKN5BR2 | 532 MHz, MICROPROCESSOR, PBGA457 |
| MK5811CMLF | 32 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MCIMX27VJP4A | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA404 |
| MCF52212AE50 | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP64 |
| MB95F104AJSPMC | 16-BIT, FLASH, 16.25 MHz, RISC MICROCONTROLLER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC56F8014 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8014E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8014MFAE | 功能描述:数字信号处理器和控制器 - DSP, DSC 16Bit DSPHC RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| MC56F8014VFAE | 功能描述:数字信号处理器和控制器 - DSP, DSC 16 BIT DSPHC BAHAMAS RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| MC56F8023 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
发布紧急采购，3分钟左右您将得到回复。