参数资料
型号: MC56F8013VFAER2
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 0-BIT, 8 MHz, OTHER DSP, PQFP32
封装: ROHS COMPLIANT, LQFP-32
文件页数: 51/125页
文件大小: 1702K
代理商: MC56F8013VFAER2
Program Map
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
31
4.3 Program Map
The Program Memory map is shown in Table 4-3.
GPIOA
25
0-2
P:$32
GPIOA
SPI
26
0-2
P:$34
SPI Receiver Full / Error
SPI
27
0-2
P:$36
SPI Transmitter Empty
SCI
28
0-2
P:$38
SCI Transmitter Empty
SCI
29
0-2
P:$3A
SCI Transmitter Idle
SCI
30
0-2
P:$3C
SCI Reserved
SCI
31
0-2
P:$3E
SCI Receiver Error
SCI
32
0-2
P:$40
SCI Receiver Full
33, 34
Reserved
I2C
35
0-2
P:$46
I2C
Timer
36
0-2
P:$48
Timer Channel 0
Timer
37
0-2
P:$4A
Timer Channel 1
(Continues next page)
Timer
38
0-2
P:$4C
Timer Channel 2
Timer
39
0-2
P:$4E
Timer Channel 3
ADC
40
0-2
P:$50
ADCA Conversion Complete
ADC
41
0-2
P:$52
ADCB Conversion Complete
ADC
42
0-2
P:$54
ADC Zero Crossing or Limit Error
PWM
43
0-2
P:$56
Reload PWM
PWM
44
0-2
P:$58
PWM Fault
SWILP
45
-1
P:$5A
SW Interrupt Low Priority
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to $0000, the first two locations of the vector table will overlay the chip reset addresses.
Table 4-3 Program Memory Map for 56F80131
Begin/End Address
Memory Allocation
P: $FF FFFF
P: $00 8800
RESERVED
P: $00 87FF
P: $00 8000
On-Chip RAM2
4KB
P: $00 7FFF
P: $00 2000
RESERVED
Table 4-2 Interrupt Vector Table Contents1 (Continued)
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
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