参数资料
型号: MC56F8155VFGE
厂商: Freescale Semiconductor
文件页数: 90/172页
文件大小: 0K
描述: IC DSP 16BIT 40MHZ 128-LQFP
标准包装: 72
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 40MHz
连通性: EBI/EMI,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 49
程序存储器容量: 256KB(128K x 16)
程序存储器类型: 闪存
RAM 容量: 8K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 16x12b
振荡器型: 外部
工作温度: -40°C ~ 105°C
封装/外壳: 128-LQFP
包装: 托盘
56F8355 Technical Data, Rev. 17
24
Freescale Semiconductor
Preliminary
RXD1
(GPIOD7)
41
Input
Input/
Output
Input,
pullup
enabled
Receive Data — SCI1 receive data input
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pullup resistor, clear bit 7 in the
GPIOD_PUR register.
TCK
115
Schmitt
Input
Input,
pulled low
internally
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the
JTAG/EOnCE port. The pin is connected internally to a pull-down
resistor.
TMS
116
Schmitt
Input
Input,
pulled high
internally
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pullup resistor.
To deactivate the internal pullup resistor, set the JTAG bit in the
SIM_PUDR register.
Note:
Always tie the TMS pin to VDD through a 2.2K resistor.
TDI
117
Schmitt
Input
Input,
pulled high
internally
Test Data Input — This input pin provides a serial input data
stream to the JTAG/EOnCE port. It is sampled on the rising edge
of TCK and has an on-chip pullup resistor.
To deactivate the internal pullup resistor, set the JTAG bit in the
SIM_PUDR register.
TDO
118
Output
In reset,
output is
disabled
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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