参数资料
型号: MC56F8346MFV60
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封装: LQFP-144
文件页数: 58/178页
文件大小: 880K
代理商: MC56F8346MFV60
56F8346 Technical Data, Rev. 15
150
Freescale Semiconductor
Preliminary
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is active in this calculation only when the chip select changes.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop
modes), T = 125ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See Figure
RESET Assertion to Address, Data and Control Signals
High Impedance
tRAZ
—21
ns
Minimum RESET Assertion Duration
tRA
16T
ns
RESET Deassertion to First External Address Output3
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 221T.
tRDA
63T
64T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
ns
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
tIDM
18T
ns
tIDM - FAST
14T
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
tIG
18T
ns
tIG - FAST
14T
Delay from IRQA Assertion (exiting Wait) to External Data
Memory access4
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
tIRI
22T
ns
tIRI - FAST
18T
Delay from IRQA Assertion to External Data Memory
Access (exiting Stop)
tIF
22T
ns
tIF - FAST
18T
IRQA Width Assertion to Recover from Stop State5
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
tIW
1.5T
ns
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