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参数资料
| 型号： | MC68030RC40C |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 40 MHz, MICROPROCESSOR, CPGA128 |
| 封装： | LEAD FREE, PGA-128 |
| 文件页数： | 10/44页 |
| 文件大小： | 499K |
| 代理商： | MC68030RC40C |
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MC68EC030 TECHNICAL DATA
MOTOROLA
Table 3. Signal Index
Signal Name
Mnemonic
Function
Function Codes
FC0–FC2
3-bit function code used to identify the address space of each bus
cycle.
Address Bus
A0–A31
32-bit address bus.
Data Bus
D0–D31
32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus
cycle.
Size
SIZ0–SIZ1
Indicates the number of bytes remaining to be transferred for this
cycle. These signals, together with A0 and A1, define the active
sections of the data bus.
Operand Cycle Start
OCS
Identical operation to that of
ECS except that OCS is asserted only
during the first bus cycle of an operand transfer
External Cycle Start
ECS
Provides an indication that a bus cycle is beginning.
Read/Write
R/
W
Defines the bus transfer as a controller read or write.
Read-Modify-Write Cycle
RMC
Provides an indicator that the current bus cycle is part of an indivisible
read-modify-write operation.
Address Strobe
AS
Indicates that a valid address is on the bus.
Data Strobe
DS
Indicates that valid data is to be placed on the data bus by an external
device or has been replaced by the MC68EC030.
Data Buffer Enable
DBEN
Provides an enable signal for external data buffers.
Data Transfer and Size
Acknowledge
DSACK0,
DSACK1
Bus response signals that indicate the requested data transfer
operation has completed. In addition, these two lines indicate the size
of the external bus port on a cycle-by-cycle basis and are used for
asynchronous transfers.
Synchronous
Termination
STERM
Bus response signal that indicates a port size of 32 bits and that data
may be latched on the next falling clock edge.
Cache Inhibit In
CIIN
Prevents data from being loaded into the MC68EC030 instruction and
data caches.
Cache Inhibit Out
CIOUT
Reflects the CI bit in ACx registers; indicates that external caches
should ignore these accesses.
Cache Burst Request
CBREQ
Indicates a burst request for the instruction or data cache.
Cache Burst
Acknowledge
CBACK
Indicates that the accessed device can operate in burst mode.
Interrupt Priority Level
IPL0–IPL2
Provides an encoded interrupt level to the controller.
Interrupt Pending
IPEND
Indicates that an interrupt is pending.
Autovector
AVEC
Requests an autovector during an interrupt acknowledge cycle.
Bus Request
BR
Indicates that an external device requires bus mastership.
Bus Grant
BG
Indicates that an external device may assume bus mastership.
Bus Grant Acknowledge
BGACK
Indicates that an external device has assumed bus mastership.
Reset
RESET
System reset.
Halt
HALT
Indicates that the controller should suspended bus activity.
Bus Error
BERR
Indicates that an erroneous bus operation is being attempted.
Cache Disable
CDIS
Dynamically disables the on-chip cache to assist emulator support.
Pipe Refill
REFILL
Indicates when the MC68EC030 is beginning to fill pipeline.
Microsequencer Status
STATUS
Indicates the state of the microsequencer.
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