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参数资料
| 型号： | MC68030RC40C |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 40 MHz, MICROPROCESSOR, CPGA128 |
| 封装： | LEAD FREE, PGA-128 |
| 文件页数： | 7/44页 |
| 文件大小： | 499K |
| 代理商： | MC68030RC40C |
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MOTOROLA
MC68EC030 TECHNICAL DATA
1 5
SYNCHRONOUS TRANSFERS
Synchronous bus cycles are terminated by asserting
STERM, which automatically indicates that the bus
transfer is for 32 bits. Since this input is not synchronized internally, two-clock-cycle bus accesses can be
performed if the signal is valid one clock after the beginning of the bus cycle with the appropriate setup
time. However, the bus cycle may be lengthened by delaying
STERM (inserting wait states in one-clock
increments) until the device being accessed is able to terminate the cycle. After the assertion of
STERM,
these cycles may be aborted upon the assertion of
BERR, or they may be retried with the simultaneous
assertion of
BERR and HALT.
BURST READ CYCLES
The MC68EC030 provides support for burst filling of its on-chip instruction and data caches, adding to
the overall system performance. The on-chip caches are organized with a line size of four long words;
there is only one tag for the four long words in a line. Since locality of reference is present to some
degree in most programs, filling of all four entries when a single entry misses can be advantageous,
especially if the time spent filling the additional entries is minimal. When the caches are burst filled, data
can be latched by the controller in as little as one clock for each 32 bits. Burst read cycles can be
performed only when the MC68EC030 requests them (with the assertion of
CBREQ) and only when the
first cycle is a synchronous cycle as previously described. If the cache burst acknowledge (
CBACK) input
is valid at the appropriate time in the synchronous bus cycle, the controller keeps the original
AS, DS,
R/
W, address, function code, and size outputs asserted and latches 32 bits from the data bus at the end
of each subsequent clock cycle that has
STERM asserted. This procedure continues until the burst is
complete (the entire block has been transferred),
BERR is asserted in lieu of or after STERM, the cache
inhibit in (
CIIN) input is asserted, or the CBACK input is negated. The cache preloading allowed by the
bursting enables the MC68EC030 to take advantage of cost-effective DRAM technology with minimal
performance impact.
EXCEPTIONS
The types of exceptions and the exception processing sequence are discussed in the following
paragraphs.
TYPES OF EXCEPTIONS
Exceptions can be generated by either internal or external causes. The externally generated exceptions
are interrupts,
BERR, and RESET. Interrupts are requests from peripheral devices for controller action;
whereas,
BERR and RESET are used for access control and controller restart. The internally generated
exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc,
TRAPVcc, cpTRAPcc, CKH, CKH2, and DIV instructions can all generate exceptions as part of instruction
execution. Tracing behaves like a very high-priority, internally generated interrupt whenever it is
processed. The other internally generated exceptions are caused by illegal instructions, instruction
fetches from odd addresses, and privilege violations.
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For More Information On This Product,
Go to: www.freescale.com
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