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| 型号： | MC68030RC40C |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 40 MHz, MICROPROCESSOR, CPGA128 |
| 封装： | LEAD FREE, PGA-128 |
| 文件页数： | 18/44页 |
| 文件大小： | 499K |
| 代理商： | MC68030RC40C |
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MOTOROLA
MC68EC030 TECHNICAL DATA
2 5
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES
(Continued)
Num.
Characterstics
25MHz
40 MHz
Unit
Min
M a x
Min
M a x
15A8
DS Negated to AS Asserted
25
—
16
—
ns
16
Clock High to
AS, DS, R/W, DBEN, CBREQ High Impedance
—
40
—
25
ns
17
AS, DS Negated to R/W Invalid
7
—
3
—
ns
18
Clock High to R/
W High
0
20
0
14
ns
20
Clock High to R/
W Low
0
20
0
14
ns
21
R/
W High to AS Asserted
7
—
5
—
ns
22
R/
W Low to DS Asserted (Write)
47
—
24
—
ns
23
Clock High to Data-Out Valid
—
20
—
14
ns
24
Data-Out Valid to Negating Edge of
AS
5—
3
—
ns
2511
AS, DS Negated to Data-Out Invalid
7
—
3
—
ns
25A9,11
DS Negated to DBEN Negated (Write)
7
—
3
—
ns
2611
Data-Out Valid to
DS Asserted (Write)
7
—
3
—
ns
27
Data-In Valid to Clock Low (Setup)
2
—
1
—
ns
27A
Late
BERR/HALT Asserted to Clock Low (Setup)
5
—
3
—
ns
2812
AS, DS Negated to
DSACKx, BERR, HALT, AVEC Negated
(Asynchronous Hold)
0400
20
ns
28A12
Clock Low to
DSACKx, BERR, HALT, AVEC Negated
(Synchronous Hold)
8706
40
ns
2912
AS, DS Negated to Data-In Invalid (Asynchronous Hold)
0
—
0
—
ns
29A12
AS, DS Negated to Data-In High Impedance
—
40
—
25
ns
3012
Clock Low to Data-In Invalid (Synchronous Hold)
8
—
6
—
ns
30A12
Clock Low to Data-In High Impedance (Read followed by Write)
—
60
—
30
ns
312
DSACKx Asserted to Data-In Valid (Asynchronous Data Setup)
—
28
—
14
ns
31A3
DSACKx Asserted to DSACKx Valid (Skew)
—
7
—
3
ns
32
RESET Input Transition Time
—
1.5
—
1.5
Clks
33
Clock Low to
BG Asserted
0
20
0
14
ns
34
Clock Low to
BG Negated
0
20
0
14
Clks
35
BR Asserted to BG Asserted (RMC Not Asserted)
1.5
3.5
1.5
3.5
Clks
37
BGACK Asserted to BG Negated
1.5
3.5
1.5
3.5
Clks
37A6
BGACK Asserted to BR Negated
0
1.5
0
1.5
ns
39
BG Width Negated
60
—
30
—
ns
39A
BG Width Asserted
60
—
30
—
ns
40
Clock High to
DBEN Asserted (Read)
0
20
0
16
ns
41
Clock Low to
DBEN Negated (Read)
0
20
0
16
ns
42
Clock Low to
DBEN Asserted (Write)
0
20
0
16
ns
43
Clock High to
DBEN Negated (Write)
0
20
0
16
ns
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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