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参数资料
| 型号： | MC68030RC40C |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 40 MHz, MICROPROCESSOR, CPGA128 |
| 封装： | LEAD FREE, PGA-128 |
| 文件页数： | 5/44页 |
| 文件大小： | 499K |
| 代理商： | MC68030RC40C |
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MOTOROLA
MC68EC030 TECHNICAL DATA
1 3
DATA CACHE
The organization of the data cache (see Figure 7) is similar to that of the instruction cache. However, the
tag is composed of the upper 24 address bits, the four valid bits, and all three function code bits, explicitly
specifying the address space associated with each line. The data cache employs a write-through policy
with programmable write allocation of data writes— i.e., if a cache hit occurs on a write cycle, both the data
cache and the external device are updated with the new data. If a write cycle generates a cache miss, the
external device is updated, and a new data cache entry can be replaced or allocated for that address,
depending on the state of the write-allocate (WA) bit in the CACR.
F F F
CC C 3
2 2 2 2 1 1 111111110000000000
21 0 1
3 20
1
98 7 65432109876543210
COMPARATOR
TAG
1 OF 16
SELECT
VALID
TAG REPLACE
INDEX
TAG
LINE HIT
DATA FROM DATA
CACHE DATA BUS
CACHE CONTROL LOGIC
V
ACCESS ADDRESS
DATA TO EXECUTION
UNIT
ENTRY HIT
A
LONG-WORD
SELECT
CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1
AA AAAAAAAAAAAAAAAAAAAAAA
Figure 7. On-Chip Data Cache Organization
OPERAND TRANSFER MECHANISM
The MC68EC030 offers three different mechanisms by which data can be transferred into and out of the
chip. Asynchronous bus cycles, compatible with the asynchronous bus on the MC68020 and MC68030,
can transfer data in a minimum of three clock cycles; the amount of data transferred on each cycle is
determined by the dynamic bus sizing mechanism on a cycle-by-cycle basis with the data transfer and size
acknowledge (
DSACKx) signals. Synchronous bus cycles, compatible with the synchronous bus on the
MC68030, are terminated with the synchronous termination (
STERM) signal and always transfer 32-bits
of data in a minimum of two clock cycles, increasing the bus bandwidth available for other bus masters,
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For More Information On This Product,
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