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参数资料
| 型号： | MC68030RC40C |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 40 MHz, MICROPROCESSOR, CPGA128 |
| 封装： | LEAD FREE, PGA-128 |
| 文件页数： | 17/44页 |
| 文件大小： | 499K |
| 代理商： | MC68030RC40C |
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2 4
MC68EC030 TECHNICAL DATA
MOTOROLA
0.8 V
2.0 V
NOTE:
4
5
1
2
3
Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted.
The voltage swing through this range should start outside and pass through the range so that the rise or fall will be
linear between 0.8 V and 2.0 V.
Figure 10. Clock Input Timing Diagram
AC ELECTRICAL SPECIFICATIONS -- READ AND WRITE CYCLES
(VCC=5.0Vdc ± 5%; GND=0 Vdc; temperature in defined ranges; see Figures 11–16)
Num.
Characterstics
25MHz
40 MHz
Unit
Min
M a x
Min
M a x
6
Clock High to Function Code, Size,
RMC, IPEND,CIOUT,
Address Valid
0200
14
ns
6A
Clock High to
ECS, OCS Asserted
0
15
0
10
ns
6B
Function Code, Size,
RMC, IPEND, CIOUT, Address Valid to
Negating Edge of
ECS
3—
3
—
ns
7
Clock High to Function Code Size,
RMC, CIOUT, Address Data
High
Impedance
0400
25
ns
8
Clock High to Function Code Size,
RMC, IPEND, CIOUT, Address
Invalid
0—
0
—
ns
9
Clock Low to
AS, DS Asserted, CBREQ Valid
3
18
2
10
ns
9A1
AS to DS Assertion Skew (Read)
-10
10
-6
6
ns
9B14
AS Asserted to DS Asserted (Write)
27
—
16
—
ns
10
ECS Width Asserted
10
—
5
—
ns
10A
OCS Width Asserted
10
—
5
—
ns
10B7
ECS, OCS Width Negated
5
—
5
—
ns
11
Function Code, Size,
RMC, CIOUT, Address Valid to AS Asserted
(and
DS Asserted, Read)
7—
5
—
ns
12
Clock Low to
AS, DS, CBREQ Negated
0
18
0
10
ns
12A
Clock Low to
ECS/OCS Negated
0
18
0
12
ns
13
AS, DS Negated to Function Code, Size, RMC CIOUT, Address
Invalid
7—
3
—
ns
14
AS (and DS Read) Width Asserted (Asynchronous Cycle)
70
—
30
—
ns
14A11
DS Width Asserted (Write)
30
—
18
—
ns
14B
AS (and DS, Read) Width Asserted (Synchronous Cycle)
30
—
18
—
ns
15
AS, DS Width Negated
30
—
18
—
ns
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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