参数资料
| 型号： | MC68711E20VFNE2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 101/138页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 52-PLCC |
| 标准包装： | 23 |
| 系列： | HC11 |
| 核心处理器： | HC11 |
| 芯体尺寸： | 8-位 |
| 速度： | 4MHz |
| 连通性： | SCI，SPI |
| 外围设备： | POR，WDT |
| 输入/输出数： | 38 |
| 程序存储器容量： | 20KB（20K x 8） |
| 程序存储器类型： | OTP |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 数据转换器： | A/D 8x8b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 52-LCC（J 形引线） |
| 包装： | 管件 |
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MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
65
Chapter 6
Serial Communications Interface (SCI)
6.1 Introduction
The serial communications interface (SCI) is a universal asynchronous receiver transmitter (UART), one
of two independent serial input/output (I/O) subsystems in the MC68HC711D3. It has a standard
non-return to zero (NRZ) format (one start, eight or nine data, and one stop bit). Several baud rates are
available. The SCI transmitter and receiver are independent, but use the same data format and bit rate.
6.2 Data Format
The serial data format requires these conditions:
An idle line in the high state before transmission or reception of a message
A start bit, logic 0, transmitted or received, that indicates the start of each character
Data that is transmitted and received least significant bit (LSB) first
A stop bit, logic 1, used to indicate the end of a frame. A frame consists of a start bit, a character
of eight or nine data bits, and a stop bit.
A break, defined as the transmission or reception of a logic 0 for some multiple number of frames
Selection of the word length is controlled by the M bit in the SCI control register 1 (SCCR1).
6.3 Transmit Operation
The SCI transmitter includes a parallel transmit data register (SCDR) and a serial shift register that puts
data from the SCDR into serial form. The contents of the serial shift register can only be written through
the SCDR. This double-buffered operation allows a character to be shifted out serially while another
character is waiting in the SCDR to be transferred into the serial shift register. The output of the serial shift
register is applied to PD1 as long as transmission is in progress or the transmit enable (TE) bit of serial
communication control register 2 (SCCR2) is set. The block diagram, Figure 6-1, shows the transmit serial
shift register and the buffer logic at the top of the figure.
6.4 Receive Operation
During receive operations, the transmit sequence is reversed. The serial shift register receives data and
transfers it to a parallel receive data register (SCDR) as a complete word. Refer to Figure 6-2. This
double-buffered operation allows a character to be shifted in serially while another character is already in
the SCDR. An advanced data recovery scheme distinguishes valid data from noise in the serial data
stream. The data input is selectively sampled to detect receive data, and a majority voting circuit
determines the value and integrity of each bit.
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