参数资料
型号: MC68HC705C9AFNE
厂商: Freescale Semiconductor
文件页数: 67/118页
文件大小: 0K
描述: IC MCU 8BIT 44-PLCC
标准包装: 26
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 24
程序存储器容量: 16KB(16K x 8)
程序存储器类型: OTP
RAM 容量: 352 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
Capture/Compare Timer
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
52
Freescale Semiconductor
8.2 Timer Operation
The core of the capture/compare timer is a 16-bit free-running counter. The counter provides the timing
reference for the input capture and output compare functions. The input capture and output compare
functions provide a means to latch the times at which external events occur, to measure input waveforms,
and to generate output waveforms and timing delays. Software can read the value in the 16-bit
free-running counter at any time without affecting the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input capture and output compare
functions are pairs of 8-bit registers.
Because the counter is 16 bits long and preceded by a fixed divide-by-4 prescaler, the counter rolls over
every 262,144 internal clock cycles. Timer resolution with a 4-MHz crystal is 2
s.
8.2.1 Input Capture
The input capture function is a means to record the time at which an external event occurs. When the
input capture circuitry detects an active edge on the TCAP pin, it latches the contents of the timer registers
into the input capture registers. The polarity of the active edge is programmable.
Latching values into the input capture registers at successive edges of the same polarity measures the
period of the input signal on the TCAP pin. Latching values into the input capture registers at successive
edges of opposite polarity measures the pulse width of the signal.
8.2.2 Output Compare
The output compare function is a means of generating an output signal when the 16-bit counter reaches
a selected value. Software writes the selected value into the output compare registers. On every fourth
internal clock cycle the output compare circuitry compares the value of the counter to the value written in
the output compare registers. When a match occurs, the timer transfers the programmable output level
bit (OLVL) from the timer control register to the TCMP pin.
The programmer can use the output compare register to measure time periods, to generate timing delays,
or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the
TCMP pin.
8.3 Timer I/O Registers
The following I/O registers control and monitor timer operation:
Timer control register (TCR)
Timer status register (TSR)
Timer registers (TRH and TRL)
Alternate timer registers (ATRH and ATRL)
Input capture registers (ICRH and ICRL)
Output compare registers (OCRH and OCRL)
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