参数资料
型号: MC68HC705F8B
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 1.8 MHz, MICROCONTROLLER, PDIP56
封装: PLASTIC, SDIP-56
文件页数: 5/126页
文件大小: 1084K
代理商: MC68HC705F8B
MOTOROLA
11-2
MC68HC05F8
LOW POWER MODES
11
11.1.2
Timer B during Stop Mode
When Stop mode is entered, the timer B (reloadable timer) counter stops counting (the internal
processor clock is stopped) and remains at that particular count value until the Stop mode is
exited. If the exit was caused by reset, the reloadable timer is disabled. If the Stop mode is exited
by an interrupt (IRQ1, IRQ2, or keyboard interrupt), the counter resumes counting from the value
when it entered the Stop mode.
11.1.3
SPI during Stop Mode
When the Stop mode is entered, the baud rate generator driving the SPI shuts down. This stops
all master mode SPI operations, thus the master SPI is unable to transmit or receive any data. If
the STOP instruction is executed during an SPI transfer, that transfer is halted until the MCU exits
the Stop mode by an interrupt (IRQ1, IRQ2, or keyboard interrupt). If the Stop mode is exited by
a reset, the appropriate control/status bits are cleared and the SPI is disabled. If the device is in
the slave mode when the STOP instruction is executed, the slave SPI will still operate. It can still
accept data, clock information, and transmit data back to a master device, but no ags are set at
the end of the transmission until the Stop mode is exited by an interrupt. The user should be
careful when using the SPI as slave during the Stop mode because data protection features are
not active (e.g. write collision).
It should also be noted that when the MCU is in the Stop mode, the enabled output drivers (TCMP,
SDO, SDI, and SCK ports) remain active, and any sourcing currents from these outputs will be
part of the total supply current required by the device.
11.1.4
DMG during Stop Mode
When the Stop mode is entered, all counters which generate the timings for the DTMF and
Melody, and all current sources of the active lter will be shut down. The TONEOUT pin of the
DMG will be tri-stated and the TONEX pin will be at logic high. All DMG operations are halted.
11.1.5
COP during Stop Mode
If the COP system is enabled and the “kill” watchdog timer feature is not activated, the watchdog
timer will continue to run in Stop mode, and eventually time-out, causing a reset to the MCU.
If the COP system is enabled and the “kill” watchdog timer is activated, a STOP instruction will
reset the watchdog timer and disable the COP system.
If the WDTE bit is set, when the MCU exits Stop mode (by an interrupt), the COP system is
automatically enabled and the watchdog timer counter is loaded with the initial value. The COP
system remains inactive if WDTE bit is cleared.
TPG
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For More Information On This Product,
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For More Information On This Product,
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相关代理商/技术参数
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