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| 型号： | MC68HC705F8B |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 1.8 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | PLASTIC, SDIP-56 |
| 文件页数： | 68/126页 |
| 文件大小： | 1084K |
| 代理商： | MC68HC705F8B |
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MOTOROLA
5-10
MC68HC05F8
INTERRUPTS
5
ICF - Input Capture Flag
ICF is set when a proper edge has been sensed by the input capture edge
detector. It is cleared by an CPU read of the TSR (with ICF set) followed by
accessing the Input Capture register least signicant byte ($1B).
All three timer interrupt ags have corresponding enable bits (ICIE, OCIE, and TOIE) found in the
Timer Control register (TCR) at location $18. Reset clears all enable bits preventing an interrupt
from occurring. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
machine is pushed onto the stack and the interrupt mask bit in the condition code register is set.
This masks further interrupts until the present one is serviced. The service routine address is
specied by the contents of $FFF6 and $FFF7.
Refer to Section 6.1 for detailed description of Programmable Timer.
5.6
Reloadable Timer (Timer B) Interrupt
Timer B interrupt (TUF) occurs only when the timer B counter rolls over from $0001 to $0000 if the
Timer B interrupt enable bit (TBOIE in Timer B Control & Status register $22) is set.
The interrupt service routine address is specied by the contents of memory location
$FFF8-$FFF9.
Refer to Section 6.2 - Reloadable Timer B for detailed description.
5.7
SPI Interrupt
An interrupt in the serial peripheral interface (SPI) occurs when the SPI interrupt ag in the Serial
Peripheral Status register (bit 7 of address $11) is set, provided the interrupt mask bit in the
Condition Code register is cleared and the enable bit in the Serial Peripheral Control register ($10)
is enabled. When the interrupt is recognized, the current state of the CPU is pushed onto the stack
and the interrupt mask bit in the condition code register is set. This masks any further interrupt
until the present one is serviced. The SPI interrupt causes the program counter to vector to
memory location $FFF4 and $FFF5 which contains the starting address of the interrupt’s service
routine. The SPI ag is cleared by accessing the Serial Peripheral Status register (with SPIF set)
followed by a read or write of the Serial Peripheral Data register, at location $12.
Refer to Section 7 for detailed description of the Serial Peripheral Interface.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$22
TMBE
TBOIE
TCSB1
TCSB0
TUF
00-- -000
TPG
44
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