参数资料
型号: MC68HC705F8B
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 1.8 MHz, MICROCONTROLLER, PDIP56
封装: PLASTIC, SDIP-56
文件页数: 91/126页
文件大小: 1084K
代理商: MC68HC705F8B
MC68HC05F8
MOTOROLA
7-3
SERIAL PERIPHERAL INTERFACE
7
7.2.2
Serial Data Output (SDO)
Data is transmitted in MSB rst format. The state of the SDO pin will always reect the value of
the rst bit receive on the previous transmission if there was one. Prior to enabling the SPI, PD5
can be initialized to determine the beginning state if a standard output since that pin is coupled to
the last stage of the serial shift register. On the first falling edge of SCK the rst data bit to be
shifted out is presented to the output pin.
7.2.3
Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SPI pin on the falling edge of SCK. Valid data must
be present at least 112ns before the rising edge of the clock and remain valid for 112ns after the
edge.
7.3
General Operation
A block diagram of the serial peripheral interface (SPI) is shown in Figure 7-3. In a master
conguration, the master start logic originates the system clock (SCK) based on the 447.5KHz (or
the E/4) clock. This clock is also used internally to control the state controller as well as the 8-bit
shift register. As a master device, data is parallel loaded into the 8-bit shift register (from the
internal bus) during a write cycle, data is applied serially from a slave device via SDI pin to the
8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred to the read
buffer and then is made available to the internal data bus a CPU read cycle.
In a slave conguration, the slave start logic receives a system clock input (from the master
device) at SCK pin. Thus, the slave is synchronized with the master. Data from the master is
received serially at the slave SDI and loads the 8-bit shift register. After the 8-bit shift register is
loaded, its data is parallel transferred to the read buffer and then is made available to the internal
data bus during a CPU read cycle. During a write cycle, data is parallel loaded into the 8-bit shift
register from the internal data bus and then shifted out serially to the SDO pin for application to
the master device.
One point to be noted, the SCK pin needs to be externally pulled high with 10K Ohms, in order to
bias the initial states at logic high.
7.4
SPI Registers
There are three registers associated with the serial parallel interface. They are the Serial
Peripheral Control register (SPCR, location $10), the Serial Peripheral Status register (SPSR,
location $11), and the Serial Peripheral Data I/O register (SPDR, location $12). Each register are
described below.
TPG
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For More Information On This Product,
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相关代理商/技术参数
参数描述
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MC68HC705J1ACP 功能描述:IC MCU 4MHZ 1.2K OTP 20-DIP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器, 系列:HC05 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C,IrDA,LIN,SPI,UART/USART 外围设备:DMA,PDR,POR,PVD,PWM,温度传感器,WDT 输入/输出数:26 程序存储器容量:64KB(64K x 8) 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN,36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND
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