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参数资料
| 型号： | MC68HC705G1FU |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | QFP-64 |
| 文件页数： | 100/124页 |
| 文件大小： | 732K |
| 代理商： | MC68HC705G1FU |
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MC68HC05G1
MOTOROLA
8-11
SERIAL PERIPHERAL INTERFACE
8
the same sequence. If a second transfer has started while trying to clear (the previously set) SPIF
and WCOL bits with a clearing sequence containing a write to the serial peripheral data register,
only the SPIF bit will be cleared.
A collision of a write to the serial peripheral data register while an external data transfer is taking
place can occur in both the master mode and the slave mode, although with proper programming
the master device should have sufcient information to prevent this collision.
Collision in the master device is dened as a write of the serial peripheral data register while the
internal rate clock (SCK) is in the process of transfer. The signal in the SS pin in always high on
the master device.
A collision in a slave device is dened in two separate modes. One problem arises in a slave
device when the CPHA control bit is a logic zero. When CPHA is a logic zero, data is latched with
the occurrence of the rst clock transition. The slave device does not have any way of knowing
when that transition will occur; therefore, the slave device collision occurs when it attempt to write
the serial peripheral data register after its SS pin has been pulled low. The SS pin of the slave
device freezes the data in its serial peripheral data register and does not allow it to be altered if
the CPHA bit is logic zero. The master device must raise the SS pin of the slave device high
between each byte it transfer to the slave device.
The second collision mode is dened for the state of the CPHA control bit being a logic one. With
the CPHA bit set, the slave device will be receiving a clock (SCK) edge prior to the latch of the rst
data transfer. This rst clock edge will freeze the data in the slave device I/O register and allow the
most signicant bit onto the external MISO pin of the slave device. The SS pin low state enables
the slave device but the drive onto the MOSI pin does not take place until the rst data transfer
clock edge. The WCOL bit will only be set if the I/O register is accessed while a transfer is taking
place. By denition of the second collision mode, a master device might hold a slave device SS
pin low during a transfer of several bytes of data without a problem.
A special case of write collision occurs in the slave device. This happens when the master device
starts a transfer sequence (an edge of SCK for CPHA=1; or an active SS transition for CPHA=0)
at the same time the slave device CPU is writing to its serial peripheral interface data register. In
this case it is assumed that the data byte written (in the slave device serial peripheral interface) is
lost and the contents of the slave device read buffer becomes the byte that is transferred. Because
the master device receives back the last byte transmitted, the master device can detect that a fatal
write collision occurred.
Since the slave device is operating asynchronously with the master device, the WCOL bit may be
used as an indicator of a collision occurrence. This helps to alleviate the user from a strict real-time
programming effort. The WCOL bit is cleared by reset.
8.4.2.3
MODF - Mode Fault
The function of the mode fault ag bit is dened for the master mode (device). If the device is a
slave device the MODF bit will be prevented from toggling from a logic zero to a logic one;
however, this does not prevent the device from being in the slave mode with MODF bit set. The
TPG
73
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC705J1A | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC705J1ACDW | 功能描述:IC MCU 4MHZ 1.2K OTP 20-SOIC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
| MC68HC705J1ACP | 功能描述:IC MCU 4MHZ 1.2K OTP 20-DIP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
| MC68HC705J1ACPE | 功能描述:8位微控制器 -MCU HCO5 CORE+1.2K RAM + EPR RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MC68HC705J2CDW | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:MicroController, 8-Bit, 20 Pin, Plastic, SOP |
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