参数资料
型号: MC68HC705G1FU
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64
封装: QFP-64
文件页数: 67/124页
文件大小: 732K
代理商: MC68HC705G1FU
MC68HC05G1
MOTOROLA
6-1
CLOCKS
6
CLOCKS
This section describes the Phase Lock Loop and Real Time Clock.
6.1
PHASE LOCK LOOP
System clock can be obtained from either the 32KHz oscillator or the PLL. During power-up or
external reset, CPU system clock comes from the 32KHz clock. Setting CLKS of the PLL
Status/Control register (bit 7 of address $24) selects PLL clock for the CPU. PLL clock frequency
depends on FS1 & FS0; see Table 6-1. The Phase Lock Loop Indicator, PLLI (bit 0), is a read only
bit which indicates an accurate clock is ready when set. However, owing to the nite delay in
updating this PLLI, it may still be set after FS1 & FS0 are modied and the PLL clock frequency is
not yet stabled. FS1 & FS0, and CLKS are cleared during power-up or external reset.
CLKS - Clock Option
1 (set)
Use the PLL clock as the CPU clock source
0 (clear) –
Use the 32KHz clock as the CPU clock source
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
PLL Status and Control Register
$24
CLKS
FS1
FS0
STPOSC
PLLI
0000 ---u
Table 6-1 Phase Lock Loop Output Frequencies
FS1
FS0
PLL Output Clock Frequency
PO2 (Internal Bus Frequency)
0
0.328MHz
0.164MHz
0
1
2.622MHz
1.311MHz
1
0
0.656MHz
0.328MHz
1
5.244MHz
2.622MHz
TPG
43
相关PDF资料
PDF描述
MC68HC05G1B 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
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