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参数资料
| 型号： | MC68HC705P6ADW |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 129/130页 |
| 文件大小： | 1541K |
| 代理商： | MC68HC705P6ADW |
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Central Processor Unit (CPU) Core
Advance Information
MC68HC705P6A — Rev. 2.0
98
Central Processor Unit (CPU) Core
MOTOROLA
12.3.5 Condition Code Register
The CCR shown in Figure 12-1 is a 5-bit register in which four bits are
used to indicate the results of the instruction just executed. The fifth bit
is the interrupt mask. These bits can be individually tested by a program,
and specific actions can be taken as a result of their state. The condition
code register should be thought of as having three additional upper bits
that are always ones. Only the interrupt mask is affected by a reset of the
device. The following paragraphs explain the functions of the lower five
bits of the condition code register.
H — Half Carry Bit
When the half-carry bit is set, it means that a carry occurred between
bits 3 and 4 of the accumulator during the last ADD or ADC (add with
carry) operation. The half-carry bit is required for binary-coded
decimal (BCD) arithmetic operations.
I — Interrupt Mask Bit
When the interrupt mask is set, the internal and external interrupts are
disabled. Interrupts are enabled when the interrupt mask is cleared.
When an interrupt occurs, the interrupt mask is automatically set after
the CPU registers are saved on the stack, but before the interrupt
vector is fetched. If an interrupt request occurs while the interrupt
mask is set, the interrupt request is latched. Normally, the interrupt is
processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its state before the interrupt
was encountered. After any reset, the interrupt mask is set and can
only be cleared by the clear I bit (CLI), STOP, or WAIT instructions.
N — Negative Bit
The negative bit is set when the result of the last arithmetic operation,
logical operation, or data manipulation was negative. (Bit 7 of the
result was a logic one.)
The negative bit can also be used to check an often-tested flag by
assigning the flag to bit 7 of a register or memory location. Loading
the accumulator with the contents of that register or location then sets
or clears the negative bit according to the state of the flag.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC705P6AMDW | 功能描述:IC MCU 4.6K OTP 2.1MHZ 28-SOIC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 标准包装:250 系列:56F8xxx 核心处理器:56800E 芯体尺寸:16-位 速度:60MHz 连通性:CAN，SCI，SPI 外围设备:POR，PWM，温度传感器，WDT 输入/输出数:21 程序存储器容量:40KB（20K x 16） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:6K x 16 电压 - 电源 (Vcc/Vdd):2.25 V ~ 3.6 V 数据转换器:A/D 6x12b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:48-LQFP 包装:托盘 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC68HC705P6AMP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HC705P6CDW | 制造商:Motorola Inc 功能描述: |
| MC68HC705P6CP | 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: |
| MC68HC705P6ECDW | 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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