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参数资料
| 型号： | MC68HC908JL8MFAE |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
| 封装： | PLASTIC, LQFP-32 |
| 文件页数： | 47/56页 |
| 文件大小： | 648K |
| 代理商： | MC68HC908JL8MFAE |
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MC68HC908JL8SM/D
Condensed Electrical Characteristics
MC68HC908JL8MC68HC908JK8
Condensed Electrical Characteristics
For more detailed information refer to the MC68HC908JL8 Data Sheet
(Motorola document order number MC68HC908JL8/D).
5-Volt DC Electrical Characteristics
5-Volt Control Timing
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
VDD supply current
Run, fOP = 8MHz
(3), XTAL option
RC option
Wait, fOP = 8MHz
(4), XTAL option
RC option
Stop(5), –40°C to 125°C, XTAL option
RC option
IDD
—
7.5
11
3
3.5
1.5
0.5
10
13
5.5
6
3
mA
A
POR rearm voltage(6)
VPOR
0
—
100
mV
POR rise time ramp rate(7)
RPOR
0.035
—
V/ms
Monitor mode entry voltage
VTST
1.5
× V
DD
—8.5
V
Pullup resistors(8)
PTD6, PTD7
RST, IRQ, PTA0–PTA7
RPU
1.8
16
3.3
26
4.8
36
k
k
Low-voltage inhibit reset, trip falling voltage
VTRIPF
3.60
4.25
4.48
V
Low-voltage inhibit reset, trip rising voltage
VTRIPR
3.75
4.40
4.63
V
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source (fOP = 8MHz). All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. All ports configured as inputs. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 8MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all
outputs. All ports configured as inputs.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0 V.
Characteristic(1)
Symbol
Min
Max
Unit
Internal operating frequency(2)
fOP
—8
MHz
RST input pulse width low(3)
tIRL
750
—
ns
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
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