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参数资料
型号： MC68HCL05P1AP
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封装： PLASTIC, DIP-28
文件页数： 62/124页
文件大小： 3724K
代理商： MC68HCL05P1AP
NON-DISCLOSURE
AGREEMENT
REQUIRED
Interrupts
General Release Specification
MC68HC05P1A — Rev. 3.0
Interrupts
If level sensitivity is chosen, the active high state of the IRQ input can
also activate an IRQ request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the following cases:
1. Low level on the IRQ pin.
2. Falling edge on the IRQ pin with all enabled port A interrupt pins
at a high level.
3. Low level on any enabled port A interrupt pin.
4. Falling edge on any enabled port A interrupt pin with all enabled
port A interrupt pins on the IRQ pin at a high level.
This interrupt is serviced by the interrupt service routine located at the
address specified by the contents of $1FFA and $1FFB. The IRQ latch
is automatically cleared by entering the interrupt service routine.
4.5.2 Optional External Interrupts (PA0–PA7)
The IRQ interrupt can be triggered by the inputs on the PA0–PA7 port
pins if enabled by individual mask options. With pullup enabled, each
port A pin can activate the IRQ interrupt function and the interrupt
operation will be the same as for inputs to the IRQ pin. Once enabled by
mask option, each individual port A pin can be disabled as an interrupt
source if its corresponding DDR bit is configured for output mode.
NOTE:
The BIH and BIL instructions apply to the output of the logic OR function
of the enabled PA0–PA7 interrupt pins and the IRQ pin. The BIH and BIL
instructions do not exclusively test the state of the IRQ pin.
NOTE:
If enabled, the PA0–PA7 pins will cause an IRQ interrupt only if these
individual pins are configured as inputs.
4.5.3 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described
in Section 8. 16-Bit Timer. The input capture interrupt flag is located in
register TSR and its corresponding enable bit can be found in register
TCR. The I bit in the CCR must be clear for the input capture interrupt to
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