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| 型号： | MC7448HX1000NC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 49/60页 |
| 文件大小： | 0K |
| 描述： | IC MPU RISC 32BIT 360-FCCBGA |
| 标准包装： | 44 |
| 系列： | MPC74xx |
| 处理器类型： | 32-位 MPC74xx PowerPC |
| 速度： | 1.0GHz |
| 电压： | 1V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 360-BCBGA，FCCBGA |
| 供应商设备封装： | 360-FCCBGA（25x25） |
| 包装： | 托盘 |
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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor
53
System Design Information
Solving for T, the equation becomes:
9.7.5
Dynamic Frequency Switching (DFS)
The DFS feature in the MPC7448 adds the ability to divide the processor-to-system bus ratio by two or
four during normal functional operation. Divide-by-two mode is enabled by setting the HID1[DFS2] bit
in software or by asserting the DFS2 pin via hardware. The MPC7448 can be returned for full speed by
clearing HID1[DFS2] or negating DFS2. Similarly, divide-by-four mode is enabled by setting
HID1[DFS4] in software or by asserting the DFS4 pin. In all cases, the frequency change occurs in 1 clock
cycle and no idle waiting period is required to switch between modes. Note that asserting either DFS2 or
DFS4 overrides software control of DFS, and that asserting both DFS2 and DFS4 disables DFS
completely, including software control. Additional information regarding DFS can be found in the
MPC7450 RISC Microprocessor Family Reference Manual. Note that minimum core frequency
requirements must be observed when enabling DFS, and the resulting core frequency must meet the
9.7.5.1
Power Consumption with DFS Enabled
Power consumption with DFS enabled can be approximated using the following formula:
Where:
PDFS = Power consumption with DFS enabled
fDFS = Core frequency with DFS enabled
f = Core frequency prior to enabling DFS
P = Power consumption prior to enabling DFS (see Table 7)
The above is an approximation only. Power consumption with DFS enabled is not tested or guaranteed.
9.7.5.2
Bus-to-Core Multiplier Constraints with DFS
DFS is not available for all bus-to-core multipliers as configured by PLL_CFG[0:5] during hard reset. The
complete listing is shown in Table 16. Shaded cells represent DFS modes that are not available for a
particular PLL_CFG[0:5] setting. Should software or hardware attempt to transition to a multiplier that is
not supported, the device will remain at its current multiplier. For example, if a transition from
DFS-disabled to an unsupported divide-by-2 or divide-by-4 setting is attempted, the bus-to-core multiplier
will remain at the setting configured by the PLL_CFG[0:5] pins. In the case of an attempted transition from
a supported divide-by-2 mode to an unsupported divide-by-4 mode, the device will remain in divide-by-2
mode. In all cases, the HID1[PC0-5] bits will correctly reflect the current bus-to-core frequency multiplier.
nT =
VH – VL
__________
1.986
× 10–4
PDFS =
(P – PDS) + PDS
fDFS
___
f
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| MC7448HX1000ND | 功能描述:微处理器 - MPU APL8 RV2.2.1 1.0V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC7448HX1250N | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC7448 Hardware Specifications |
| MC7448HX1250NC | 功能描述:IC MPU RISC 32BIT 360-FCCBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:MPC74xx 标准包装:1 系列:MPC85xx 处理器类型:32-位 MPC85xx PowerQUICC III 特点:- 速度:1.2GHz 电压:1.1V 安装类型:表面贴装 封装/外壳:783-BBGA，FCBGA 供应商设备封装:783-FCPBGA（29x29） 包装:托盘 |
| MC7448HX1250ND | 功能描述:微处理器 - MPU APL8 RV2.2.1 1.1V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC7448HX1267NC | 功能描述:IC MPU RISC 32BIT 360-FCCBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:MPC74xx 标准包装:1 系列:MPC85xx 处理器类型:32-位 MPC85xx PowerQUICC III 特点:- 速度:1.2GHz 电压:1.1V 安装类型:表面贴装 封装/外壳:783-BBGA，FCBGA 供应商设备封装:783-FCPBGA（29x29） 包装:托盘 |
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