参数资料
型号: MC8610PX1066JB
厂商: Freescale Semiconductor
文件页数: 18/96页
文件大小: 0K
描述: MPU E600 CORE 1066MHZ 783-PBGA
标准包装: 36
系列: MPC86xx
处理器类型: 32-位 MPC86xx PowerPC
速度: 1.066GHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
25
2.4.5
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes see the specific section of this
document.
2.5
RESET Initialization
Table 12 describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8610.
Table 13 provides the PLL lock times.
2.6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8610. Note that DDR
SDRAM is GVDD = 2.5 V and DDR2 SDRAM is GVDD = 1.8 V.
Table 12. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
μs
Minimum assertion time for SRESET
3
SYSCLKs
1
Platform PLL input setup time with stable SYSCLK before HRESET
negation
100
μs2
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
4
SYSCLKs
1
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
2
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configs
with respect to negation of HRESET
5
SYSCLKs
1
Notes:
1. SYSCLK is he primary clock input for the device.
2. This is related to HRESET assertion time.
Table 13. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times (platform, PCI and e600 core)
100
μs1
Notes:
1. The PLL lock time for the e600 core PLL requires an additional 255 platform clock cycles.
相关PDF资料
PDF描述
345-012-523-204 CARDEDGE 12POS DUAL .100 GREEN
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