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| 型号： | MC8610PX1066JB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 65/96页 |
| 文件大小： | 0K |
| 描述： | MPU E600 CORE 1066MHZ 783-PBGA |
| 标准包装： | 36 |
| 系列： | MPC86xx |
| 处理器类型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.066GHz |
| 电压： | 1V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 783-BBGA，FCBGA |
| 供应商设备封装： | 783-FCPBGA（29x29） |
| 包装： | 托盘 |
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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
68
2.18.5
Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 42 is specified using the passive compliance/test measurement load (see Figure 43) in place of
any real PCI Express RX component.
Note: In general, the minimum receiver eye diagram measured with the compliance/test measurement load (see Figure 43) will
be larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real PCI Express
component. The degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon parasitic
characteristics which cause the real PCI Express component to vary in impedance from the compliance/test measurement load.
The input receiver eye diagram is implementation specific and is not specified. RX component designer should provide
additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in Figure 42) expected at
the input receiver based on some adequate combination of system simulations and the return loss measured looking into the RX
package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
LTX-SKEW
Total skew
20
ns
Skew across all lanes on a link. This includes variation
in the length of SKP ordered set (e.g., COM and one
to five symbols) at the RX as well as any delay
differences arising from the interconnect itself.
Notes:
1.)No test load is necessarily associated with this value.
2.)Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 43 should be used
as the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 42). If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must
be used as a reference for the eye diagram.
3.)A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in
which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any
250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point
in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must
be used as the reference for the eye diagram.
4.)The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to
300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The
reference impedance for return loss measurements for is 50
Ω to ground for both the D+ and D– line (that is, as measured by
a Vector Network Analyzer with 50-
Ω probes—see Figure 43). Note that the series capacitors CTX is optional for the return
loss measurement.
5.)Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
6.)The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the RX ground.
7.)It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated
data.
Table 50. Differential Receiver (RX) Input Specifications (continued)
Symbol
Parameter
Min
Nom
Max
Units
Comments
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC8610PX1066JZ | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8610 Integrated Host Processor Hardware Specifications |
| MC8610PX1067G | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8610PX1067J | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8610PX1333JB | 功能描述:微处理器 - MPU REV 1.1 8610 1.025V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC8610PX1333JZ | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8610 Integrated Host Processor Hardware Specifications |
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