- 您现在的位置：买卖IC网 > PDF目录3944 > MC8610PX1066JB (Freescale Semiconductor)MPU E600 CORE 1066MHZ 783-PBGA PDF资料下载
参数资料
| 型号： | MC8610PX1066JB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 6/96页 |
| 文件大小： | 0K |
| 描述： | MPU E600 CORE 1066MHZ 783-PBGA |
| 标准包装： | 36 |
| 系列： | MPC86xx |
| 处理器类型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.066GHz |
| 电压： | 1V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 783-BBGA，FCBGA |
| 供应商设备封装： | 783-FCPBGA（29x29） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Pin Assignments and Reset States
Freescale Semiconductor
14
ASLEEP
cfg_core_speed
B26
—
OVDD
13
MSRCID0
cfg_mem_debug
Y20
—
BVDD
MDVAL
cfg_boot_vector
AC20
—
BVDD
Notes:
1. Multi-pin signals such as LDP[0:3] have their physical package pin numbers listed in order corresponding to the signal names.
2. Stub series terminated logic type pins.
3. All SSI signals are multiplexed with eLBC signals.
4. Low voltage transistor-transistor logic (LVTTL) type pins.
5. DIU_LD[23:16] = RED[7:0].
DIU_LD[15:8] = GREEN[7:0].
DIU_LD[7:0] = BLUE[7:0].
6. The pins for the SSI interface on the device are multiplexed with certain eLBC signals, which have the ability to operate at a
different voltage than the other standard I/O signals. If the device is configured such that the eLBC uses a different voltage
than standard I/O and an SSI port on the device is used, then level shifters are required on the SSI signals to ensure they
correctly interface to other devices on the board at the proper voltage.
7. This pin should be pulled to ground with a 100-
Ω resistor.
8. This pin should be pulled to ground with a 200-
Ω resistor.
9. These pins should be left floating.
10.This is a SerDes PLL/DLL digital test signal and is only for factory use.
11.This is a SerDes PLL/DLL analog test signal and is only for factory use.
12.This pin should be pulled down if the platform frequency is 400 MHz or below.
13.This pin should be pulled down if the core frequency is 800 MHz or below.
14.MSRCID[1:2], DIU_LD[5:6] and TRIG_OUT/READY should NOT be pulled down (or driven low) during reset.15. The pins in
this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when the
processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ω pull-down
resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down
the value of the net at reset, then a pullup or active driver is needed.
16.These pins should be left floating.
17.Must be tied low if unused.
18.This output is actively driven during reset rather than being tri-stated during reset.
19.MDIC[0] should be connected to ground with an 18-
Ω resistor ± 1 Ω and MDIC[1] should be connected to GVDD with an 18-Ω
resistor ± 1
Ω. These pins are used for automatic calibration of the DDR IOs.
20.This pin is a reset configuration pin and appears again in the Reset Configuration Signals section of this table. See the Reset
Configuration Signals section of this table for config name and connection details.
21.Recommend a weak pull-up resistor (1–10 k
Ω) be placed from this pin to its power supply.
22.This multiplexed pin has input status in one mode and output in another.
23.This pin is a multiplexed signal for different functional blocks and appears more than once in this table.
24.For systems which boot from local bus (GPCM)-controlled flash, a pullup on LGPL4 is required.
25.This pin is open drain signal.
26.These are test signals for factory use only and must be pulled up (100
Ω to 1 kΩ) to OVDD for normal machine operation.
27.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
28.These pins are connected to the power/ground planes internally and may be used by the core power supply to improve
tracking and regulation.
Table 1. Signal Reference by Functional Block (continued)
Name1
Package Pin Number
Pin Type
Power Supply
Notes
相关PDF资料 |
PDF描述 |
|---|---|
| 345-012-523-204 | CARDEDGE 12POS DUAL .100 GREEN |
| 345-012-523-202 | CARDEDGE 12POS DUAL .100 GREEN |
| 345-012-523-201 | CARDEDGE 12POS DUAL .100 GREEN |
| 345-012-521-804 | CARDEDGE 12POS DUAL .100 GREEN |
| 345-012-521-802 | CARDEDGE 12POS DUAL .100 GREEN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC8610PX1066JZ | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8610 Integrated Host Processor Hardware Specifications |
| MC8610PX1067G | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8610PX1067J | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8610PX1333JB | 功能描述:微处理器 - MPU REV 1.1 8610 1.025V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC8610PX1333JZ | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8610 Integrated Host Processor Hardware Specifications |
发布紧急采购，3分钟左右您将得到回复。