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参数资料
| 型号： | MC8610TPX1066JZ |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, PBGA783 |
| 封装： | 29 X 29 MM, PLASTIC, FCBGA-783 |
| 文件页数： | 13/96页 |
| 文件大小： | 1237K |
| 代理商： | MC8610TPX1066JZ |
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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
20
Figure 3 illustrates the power up sequence as described above.
Figure 3. MPC8610 Power Up Sequencing
VDD_PLAT, AVDD_PLAT
OVDD
Time
2.5 V
3.3 V
0
DC
P
o
w
e
rSupp
ly
V
o
lt
age
Reset
Configuration Pins
HRESET (& TRST)
Asserted for
100
μs4
VDD Stable
Power Supply Ramp Up 2
Notes:
1. Dotted waveforms correspond to optional supply values for a specified power supply. See Table 3.
2. Ther recommended maximum ramp up time for power supplies is 20 milliseconds.
3. Refer to Section 2.5, “RESET Initialization” for additional information on PLL relock and reset signal
assertion timing requirements.
4. Refer to Table 9 for additional information on reset configuration pin setup timing requirements. In
addition see Figure 53 regarding HRESET and JTAG connection details including TRST.
5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles.
6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration
inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles
after HRESET has negated (hold requirement). See Section 2.5, “RESET Initialization,” for more
information on setup and hold time of reset configuration signals.
7. The rail for VDD_PLAT, AVDD_PLAT, VDD_Core, AVDD_Core, AVDD_PCI, SnVDD, XnVDD, and SDnAVDD
must reach 90% of its value before the rail for GVDD and MVREF reaches 10% of its value.
8. SYSCLK must be driven only AFTER the power for the various power supplies is stable.
9. The reset configuration signals for DRAM types must be valid before HRESET is asserted.
e6005
AVDD_PCI, SnVDD, XnVDD
VDD_Core, AVDD_Core
SD
nAVDD
1.8 V
GVDD, = 1.8/2.5 V
MVRE
F
SYSCLK8 (not drawn to scale)
7
PLL
9
Cycles Setup and Hold Time 6
100 s Platform PLL
Relock Time3
1.0 V
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