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| 型号： | MC8610TPX1066JZ |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, PBGA783 |
| 封装： | 29 X 29 MM, PLASTIC, FCBGA-783 |
| 文件页数： | 59/96页 |
| 文件大小： | 1237K |
| 代理商： | MC8610TPX1066JZ |
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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
62
2.17.3
SerDes Transmitter and Receiver Reference Circuits
Figure 40 shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 40. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express) in this
document based on the application usage:”
Note that external AC Coupling capacitor is required for the above serial transmission protocols with the capacitor value defined
in specification of each protocol section.
2.18
PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8610.
2.18.1
DC Requirements for PCI Express SD
n_REF_CLK and
SD
n_REF_CLK
For more information, see Section 2.17.2, “SerDes Reference Clocks.”
2.18.2
AC Requirements for PCI Express SerDes Clocks
Table 48 lists AC requirements.
2.18.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
Table 48. SD
n_REF_CLK and SDn_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typ
Max
Units
tREF
REFCLK cycle time
—
10
—
ns
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles
——
100
ps
tREFPJ
Phase jitter. Deviation in edge location with respect to mean
edge location
–50
—
50
ps
50
Ω
50
Ω
Receiver
Transmitter
SD1_TX
n or
SD2_TX
n
SD1_TX
n or
SD2_TX
n
SD1_RX
n or
SD2_RX
n
SD1_RX
n or
SD2_RX
n
50
Ω
50
Ω
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