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| 型号： | MC8610TPX1066JZ |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, PBGA783 |
| 封装： | 29 X 29 MM, PLASTIC, FCBGA-783 |
| 文件页数： | 66/96页 |
| 文件大小： | 1237K |
| 代理商： | MC8610TPX1066JZ |
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Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
69
NOTE
The reference impedance for return loss measurements is 50
Ω to ground for both the D+
and D– line (i.e., as measured by a vector network analyzer with 50-
Ω probes—see
Figure 43). Note that the series capacitors, CTX, are optional for the return loss
measurement.
Figure 42. Minimum Receiver Eye Timing and Voltage Compliance Specification
2.18.5.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package
pins, into a test/measurement load shown in Figure 43.
NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary.
Figure 43. Compliance Test/Measurement Load
2.19
JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8610.
2.19.1
JTAG DC Electrical Characteristics
Table 51 provides the JTAG DC electrical characteristics for the JTAG interface.
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
TX
Silicon
+ Package
C = CTX
R = 50
Ω
R = 50
Ω
D+ Package
Pin
D– Package
Pin
D+ Package
Pin
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