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参数资料
| 型号： | MC88915TFN70 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 3/18页 |
| 文件大小： | 401K |
| 代理商： | MC88915TFN70 |
MC88915T
36
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915TFN160 (Continued)
Table 21. AC Characteristics (TA = 0°C to +70°C, VCC = 5.0 V ± 5%, Load = 50 Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
Condition
tRISE/FALL
Outputs
Rise/Fall Time, All Outputs
(Between 0.2 VCC and 0.8 VCC)
1.0
2.5
ns
Into a 50
Load
Terminated to VCC/2
tRISE/FALL
2X_Q Output
Rise/Fall Time
0.5
1.6
ns
tRISE: 0.8 V – 2.0 V
tFALL: 2.0 V – 0.8 V
tPULSEWIDTH
(Q0–Q4, Q5, Q/2)
Output Pulse Width: Q0, Q1, Q2, Q4, Q4,
Q5, Q/2 @ VCC/2
0.5 tCYCLE – 0.52 0.5 tCYCLE + 0.52
ns
Into a 50
Load
Terminated to VCC/2
tPULSEWIDTH
(2X_Q Output)
Output Pulse Width:
80 MHz
2X_Q @ 1.5 V
100 MHz
133 MHz
160 MHz
0.5 tCYCLE – 0.7
0.5 tCYCLE – 0.5
TBD
0.5 tCYCLE + 0.7
0.5 tCYCLE + 0.5
TBD
ns
tPD1
SYNC Feedback
1. TCYCLE in this spec is 1/Frequency at which the particular output is running.
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1
and FEEDBACK Input Pins)
(With 1 M
from RC1 to An VCC)
ns
Detailed Explanation
2. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
133 MHz
160 MHz
–1.05
–0.9
–0.25
–0.10
tCYCLE
(2x_Q Output)
Cycle-to-Cycle Variation
133 MHz
160 MHz
tCYCLE – 300 ps
tCYCLE + 300 ps
tSKEWr3
(Rising)4
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With VCC fully powered on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 F, tLOCK minimum is with
C1 = 0.01
F.
Output-to-Output Skew Between Outputs Q0–Q4,
Q/2 (Rising Edges Only)
—
500
ps
All Outputs into a Matched
50
Load Terminated to
VCC/2
tSKEWf3
(Falling)
Output-to-Output Skew Between Outputs Q0–Q4
(Falling Edges Only)
—
500
ps
All Outputs into a Matched
50
Load Terminated to
VCC/2
tSKEWall3
Output-to-Output Skew 2X_Q, Q/2, Q0–Q4 Rising,
Q5 Falling
—
750
ps
All Outputs into a Matched
50
Load Terminated to
VCC/2
tLOCK4
Time Required to Acquire Phase-Lock from Time
SYNC Input Signal is Received
1.0
10
ms
Also Time to LOCK
Indicator High
tPZL5
5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when “MC” status is
reached.
Output Enable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
3.0
14
ns
Measured with the PLL_EN
Pin Low
tPHZ, tPLZ5
Output Disable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
3.0
14
ns
Measured with the PLL_EN
Pin Low
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