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| 型号： | MC88915TFN70 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 9/18页 |
| 文件大小： | 401K |
| 代理商： | MC88915TFN70 |
MC88915T
42
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Figure 8. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T
Notes Concerning Loop Filter and Board Layout Issues
1.
Figure 8 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter-free operation:
a.
All loop filter and analog isolation components should
be tied as close to the package as possible. Stray
current passing through the parasitics of long traces
can cause undesirable voltage transients at the RC1
pin.
b.
The 47
resistors, the 10 F low frequency bypass
capacitor, and the 0.1
F high frequency bypass
capacitor form a wide bandwidth filter minimizing the
88915T’s sensitivity to voltage transients from the
system digital VCC supply and ground planes. This
filter will typically ensure a 100 mV step deviation on
the digital VCC supply, causing no more than a 100 ps
phase deviation o the 88915T outputs. A 250 mV step
deviation on VCC using the recommended filter
values should cause no more than 250 ps phase
deviation; if a 25
F bypass capacitor is used (instead
of 10
F) a 250 mV VCC step should cause no more
than a 100 ps phase deviation.
If good bypass techniques are used on a board
design near components potentially causing digital
VCC and ground noise, the above described VCC step
deviations should not occur at the 88915T’s digital
VCC supply. The purpose of the bypass filtering
scheme shown in Figure 8 is to give the 88915T
additional protection from the power supply and
ground plane transients potentially occurring in a high
frequency, high speed digital system.
c.
There are no special requirements set forth for the
loop filter resistors (1.0 M
and 330 ). The loop filter
capacitor (0.1
F) can be a ceramic chip capacitor,
the same as a standard bypass capacitor.
d.
The 1.0 M reference resistor injects current into the
internal charge pump of the PLL, causing a fixed
offset between the outputs and the SYNC input. This
also prevents excessive jitter caused by inherent PLL
dead-band. If the VCO (2X_Q output) is running
above 40 MHz, the 1.0 M
resistor provides the
correct amount of current injection into the charge
pump
(2–3
A). For the TFN55, 70 or 100, if the VCO is
running below 40 MHz, a 1.5 M
reference resistor
should be used (instead of 1 M
).
2.
In addition to the bypass capacitors used in the analog
filter of Figure 8, there should be a 0.1
F bypass
capacitor between each of the other (digital) four VCC pins
and the board ground plane. This will reduce output
switching noise caused by the 88915T outputs. In addition
to reducing potential for noise in the “analog” section of
the chip. These bypass capacitors should also be tied as
close to the 88915T package as possible.
10
F LOW
FREQUENCY
BYPASS
0.1
F HIGH
FREQUENCY
BYPASS
1 M
330
47
47
BOARD VCC
0.1
F (LOOP
FILTER CAP)
BOARD GND
8
ANALOG VCC
RC1
ANALOG GND
9
10
ANALOG LOOP FILTER/VCO
SECTION OF THE MC88915T
28-PIN PLCC PACKAGE (NOT
DRAWN TO SCALE)
A separate analog power supply is not necessary and
should not be used. Following these prescribed guidelines
is all that is necessary to use the MC88915T in a normal
digital environment.
NOTE:
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| MC88916DW80 | 功能描述:IC DRIVER CLK PLL 80MHZ 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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