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参数资料
| 型号： | MC88921DW |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88921 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | SOIC-20 |
| 文件页数： | 5/11页 |
| 文件大小： | 544K |
| 代理商： | MC88921DW |
MC88921
TIMING SOLUTIONS
BR1333 — REV 5
3
MOTOROLA
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Limits
Unit
VCC
Supply Voltage
5.0
±10%
V
Vin
DC Input Voltage
0 to VCC
V
Vout
DC Output Voltage
0 to VCC
V
TA
Ambient Operating Temperature
0 to 70
°C
ESD
Static Discharge Voltage
> 1500
V
DC CHARACTERISTICS (TA = –40°C to 85°C; VCC = 5.0V ± 5%)
Symbol
Parameter
VCC
Guaranteed Limits
Unit
Condition
VIH
Minimum High Level Input Voltage
4.75
5.25
2.0
V
VOUT = 0.1V or
VCC – 0.1V
VIL
Minimum Low Level Input Voltage
4.75
5.25
0.8
V
VOUT = 0.1V or
VCC – 0.1V
VOH
Minimum High Level Output Voltage
4.75
5.25
4.01
4.51
V
VIN = VIH or VIL
IOH
–36mA
VOL
Minimum Low Level Output Voltage
4.75
5.25
0.44
V
VIN = VIH or VIL
IOH
+36mA
1
+36mA
IIN
Maximum Input Leakage Current
5.25
±1.0
A
VI = VCC, GND
ICCT
Maximum ICC/Input
5.25
2.0 2
mA
VI = VCC – 2.1V
IOLD
Minimum Dynamic3 Output Current
5.25
88
mA
VOLD = 1.0V Max
IOHD
5.25
–88
mA
VOHD = 3.85 Min
ICC
Maximum Quiescent Supply Current
5.25
750
A
VI = VCC, GND
1. IOL is +12mA for the LOCK output.
2.
The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration 2.0ms, one output loaded at a time.
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Minimum
Maximum
Unit
tRISE/FALL
SYNC Input
Rise/Fall Time, SYNC Input
From 0.8V to 2.0V
—
5.0
ns
tCYCLE,
SYNC Input
Input Clock Period
SYNC Input
1
f2X_Q 4
200
ns
Duty Cycle
Duty Cycle, SYNC Input
50%
± 25%
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC88921
Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature
NETCOM
IDT Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88921
3
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