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参数资料
| 型号： | MC88921DW |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88921 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | SOIC-20 |
| 文件页数： | 6/11页 |
| 文件大小： | 544K |
| 代理商： | MC88921DW |
MC88921
MOTOROLA
TIMING SOLUTIONS
BR1333 — REV 5
4
Figure 1. MC88921 Logic Block Diagram
Q
R
D
Q0
VCO
CH
PUMP
PFD
SYNC1
PLL_EN
MR
POWER–ON
RESET
01
LOCK INDICATOR
2X_Q
LOCK
Q
R
D
Q1
Q
R
D
Q2
Q
R
D
“Dummy” Flip–Flop to Maintain
Phase–Locked Operation
Q
R
D
Q3
Q
R
D
Q
RC1
÷2
0
1
FBSEL
Q/2
FREQUENCY SPECIFICATIONS (TA = –40°C to 85°C; VCC = 5.0V ± 5%)
Symbol
Parameter
Guaranteed Minimum
Unit
Fmax (2X_Q)
Maximum Operating Frequency, 2X_Q Output
66
MHz
Fmax (‘Q’)
Maximum Operating Frequency,
Q0–Q3 Outputs
33
MHz
1. Maximum Operating Frequency is guaranteed with the 88921 in a phase–locked condition, and all outputs loaded at 50pF.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC88921
Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature
NETCOM
IDT Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88921
4
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