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| 型号： | MC9328MXSVP10 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 45/74页 |
| 文件大小： | 0K |
| 描述： | IC MCU I.MXS 100MHZ 225-MAPBGA |
| 标准包装： | 160 |
| 系列： | i.MXS |
| 核心处理器： | ARM9 |
| 芯体尺寸： | 32-位 |
| 速度： | 100MHz |
| 连通性： | EBI/EMI，I²C，SPI，SSI，UART/USART，USB |
| 外围设备： | DMA，I²S，LCD，POR，PWM，WDT |
| 输入/输出数： | 97 |
| 程序存储器类型： | ROMless |
| 电压 - 电源 (Vcc/Vdd)： | 1.7 V ~ 3.3 V |
| 振荡器型： | 外部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 225-LFBGA |
| 包装： | 托盘 |
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Signals and Connections
MC9328MXS Technical Data, Rev. 3
Freescale Semiconductor
5
CSD1
SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by
programming the system control register. By default, CSD1 is selected, so it can be used as boot
chip-select by properly configuring BOOT [3:0] input pins.
RAS
SDRAM Row Address Select signal
CAS
SDRAM Column Address Select signal
SDWE
SDRAM Write Enable signal
SDCKE0
SDRAM Clock Enable 0
SDCKE1
SDRAM Clock Enable 1
SDCLK
SDRAM Clock
RESET_SF
Not Used
Clocks and Resets
EXTAL16M
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut
down.
XTAL16M
Crystal output
EXTAL32K
32 kHz crystal input
XTAL32K
32 kHz crystal output
CLKO
Clock Out signal selected from internal clock signals.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
POR
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
JTAG
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
DMA
DMA_REQ
DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY.
BIG_ENDIAN
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven
logic-low at reset, the external chip-select space will be configured to little endian. This input must not
change state after power-on reset negates or during chip operation.
Table 2. i.MXS Signal Descriptions (Continued)
Signal Name
Function/Notes
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC9328MXSVP10 | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MXSVP10R2 | 功能描述:处理器 - 专门应用 REDUCED FEATURE CORSICA RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MC932L | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC933 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:INTEGRATED CIRCUITS |
| MC933F | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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