参数资料
型号: MC9328MXSVP10
厂商: Freescale Semiconductor
文件页数: 53/74页
文件大小: 0K
描述: IC MCU I.MXS 100MHZ 225-MAPBGA
标准包装: 160
系列: i.MXS
核心处理器: ARM9
芯体尺寸: 32-位
速度: 100MHz
连通性: EBI/EMI,I²C,SPI,SSI,UART/USART,USB
外围设备: DMA,I²S,LCD,POR,PWM,WDT
输入/输出数: 97
程序存储器类型: ROMless
电压 - 电源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 225-LFBGA
包装: 托盘
Functional Description and Application Information
MC9328MXS Technical Data, Rev. 3
Freescale Semiconductor
57
4.7
Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in
Figure 42 and the parameters are listed in Table 22.
Figure 42. PWM Output Timing Diagram
T8
SCLK to valid LD data
-3
3
ns
T9
End of HSYN idle2 to VSYN edge
(for non-display region)
22
Ts
T9
End of HSYN idle2 to VSYN edge
(for Display region)
11
Ts
T10
VSYN to OE active (Sharp = 0) when VWAIT2 = 0
1
Ts
T10
VSYN to OE active (Sharp = 1) when VWAIT2 = 0
2
Ts
Note:
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 41, all 3 signals
are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period.
In Figure 41, SCLK is always active.
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Symbol
Description
Minimum
Corresponding Register Value
Unit
System Clock
2a
1
PWM Output
3b
2b
3a
4b
4a
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