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| 型号： | MCF5233CVM150 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | MAPBGA-256 |
| 文件页数： | 16/76页 |
| 文件大小： | 2665K |
| 代理商： | MCF5233CVM150 |
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MOTOROLA
MCF523x Integrated Microprocessor Hardware Specifications
23
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Primary Functions
2.2.8
Ethernet Module (FEC) Signals
The following signals are used by the Ethernet module for data and clock signals. Some of these signals are
muxed with eTPU channels on the MCF5235 and dedicated on the other members of the family that have
an Ethernet Module.
Table 10. Ethernet Module (FEC) Signals
Signal Name
Abbreviation
Function
I/O
Management Data
EMDIO
Transfers control information between the external PHY and the
media-access controller. Data is synchronous to EMDC. Applies to MII
mode operation. This signal is an input after reset. When the FEC is
operated in 10Mbps 7-wire interface mode, this signal should be
connected to VSS.
This pin can also be configured as GPIO port AS5 or UART2 receive
data U2RXD.
I/O
Management Data
Clock
EMDC
In Ethernet mode, EMDC is an output clock which provides a timing
reference to the PHY for data transfers on the EMDIO signal. Applies
to MII mode operation.
This pin can also be configured as UART2 transmit data U2TXD or I2C
clock I2C_SCL.
O
Transmit Clock
ETXCLK
Input clock which provides a timing reference for ETXEN, ETXD[3:0]
and ETXER
I
Transmit Enable
ETXEN
Indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the
first ETXCLK following the final nibble of the frame.
O
Transmit Data 0
ETXD0
ETXD0 is the serial output Ethernet data and is only valid during the
assertion of ETXEN. This signal is used for 10-Mbps Ethernet data. It
is also used for MII mode data in conjunction with ETXD[3:1].
O
Collision
ECOL
Asserted upon detection of a collision and remains asserted while the
collision persists. This signal is not defined for full-duplex mode.
I
Receive Clock
ERXCLK
Provides a timing reference for ERXDV, ERXD[3:0], and ERXER.
I
Receive Data Valid
ERXDV
Asserting the receive data valid (ERXDV) input indicates that the PHY
has valid nibbles present on the MII. ERXDV should remain asserted
from the first recovered nibble of the frame through to the last nibble.
Assertion of ERXDV must start no later than the SFD and exclude any
EOF.
I
Receive Data 0
ERXD0
ERXD0 is the Ethernet input data transferred from the PHY to the
media-access controller when ERxDV is asserted. This signal is used
for 10-Mbps Ethernet data. This signal is also used for MII mode
Ethernet data in conjunction with ERXD[3:1].
I
Carrier Receive Sense
ECRS
When asserted, indicates that transmit or receive medium is not idle.
Applies to MII mode operation.
This pin can also be configured and UART2 receive U2RXD or I2C
data I2C_SDA.
I
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