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参数资料
| 型号： | MCF5233CVM150 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | MAPBGA-256 |
| 文件页数： | 6/76页 |
| 文件大小： | 2665K |
| 代理商： | MCF5233CVM150 |
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14
MCF523x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of a given controller provide a
programmable level [1-7] and priority within the level.
1.3.19 DMA Controller
The Direct Memory Access (DMA) Controller Module provides an efficient way to move blocks of data
with minimal processor interaction. The DMA module provides four channels (DMA0-DMA3) that allow
byte, word, longword or 16-byte burst line transfers. These transfers are triggered by software explicitly
setting a DCRn[START] bit. Other sources include the DMA timer, external sources via the DREQ signal,
UARTs, and the eTPU. The DMA controller supports single or dual address to off-chip devices or dual
address to on-chip devices.
1.3.20 External Bus Interface (EBI)
The external bus interface handles the transfer of information between the core and memory, peripherals, or
other processing elements in the external address space. Features have been added to support external Flash
modules, for secondary wait states on reads and writes, and a signal to support Active-Low Address Valid
(a signal on most Flash memories).
Programmable chip-select outputs provide signals to enable external memory and peripheral circuits,
providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting
address must be on a boundary that is a multiple of the block size. Each chip select can be configured to
provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data
bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for
protection from user mode access or read-only access.
1.3.21 SDRAM Controller
The SDRAM controller provides all required signals for glueless interfacing to a variety of
JEDEC-compliant SDRAM devices. SD_SRAS/SD_SCAS address multiplexing is software configurable
for different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the
address and data buses, SD_SRAS, SD_SCAS, SDWE, SD_CS[1:0] and SD_CKE are dedicated SDRAM
signals. <<<Is SD_CKE active low?>>>
1.3.22 Reset
The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the
system, and keep track of what caused the last reset. The power management registers for the internal
low-voltage detect (LVD) circuit are implemented in the reset module. There are six sources of reset:
External
Power-on reset (POR)
Watchdog timer
Phase locked-loop (PLL) loss of lock
PLL loss of clock
Software
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MCF5233CVM150J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
| MCF5234 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Microprocessor Hardware Specification |
| MCF5234256MAPBGA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Microprocessor Hardware Specification |
| MCF5234CVM100 | 功能描述:微处理器 - MPU MCF5234 V2CORE 64KSRAM RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MCF5234CVM100J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
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