- 您现在的位置：买卖IC网 > PDF目录132981 > MCF5233CVM150 (MOTOROLA INC) 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 PDF资料下载
参数资料
| 型号： | MCF5233CVM150 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | MAPBGA-256 |
| 文件页数： | 3/76页 |
| 文件大小： | 2665K |
| 代理商： | MCF5233CVM150 |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页
MOTOROLA
MCF523x Integrated Microprocessor Hardware Specifications
11
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers
(with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register),
and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through the
dedicated debug serial communication channel or from the processor’s supervisor mode programming
model. The breakpoint registers can be configured to generate triggers by combining the address, data, and
PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to
generate a processor halt or initiate a debug interrupt exception.
To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug data
(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data,
and branch target addresses defining processor activity at the CPU’s clock rate.
The integration of the eTPU on the MCF523x family marks the first time that ColdFire and Nexus debug
subsystems have been present in a single device. The eTPU’s Nexus functionality has been merged into the
standard ColdFire debug model. This includes access to the eTPU Nexus debug registers via the standard
ColdFire BDM serial interface or the processor WDEBUG instruction and run/halt cross triggering
capability between eTPU Nexus and ColdFire BDM.
1.3.6
JTAG
The MCF523x supports circuit board test strategies based on the Test Technology Committee of IEEE and
the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state
controller, an instruction register, and three test registers (a 1-bit bypass register, a 330-bit boundary-scan
register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register.
Test logic, implemented using static logic design, is independent of the device system logic.
The MCF523x implementation can do the following:
Perform boundary-scan operations to test circuit board electrical continuity
Sample MCF523x system pins during operation and transparently shift out the result in the
boundary scan register
Bypass the MCF523x for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
1.3.7
On-chip Memories
1.3.7.1
Cache
The 8-Kbyte cache can be configured into one of three possible organizations: an 8-Kbyte instruction cache,
an 8-Kbyte data cache or a split 4-Kbyte instruction/4-Kbyte data cache. The configuration is
software-programmable by control bits within the privileged Cache Configuration Register (CACR). In all
configurations, the cache is a direct-mapped single-cycle memory, organized as 512 lines, each containing
16 bytes of data. The memories consist of a 512-entry tag array (containing addresses and control bits) and
a 8-Kbyte data array, organized as 2048
× 32 bits.
If the desired address is mapped into the cache memory, the output of the data array is driven onto the
ColdFire core's local data bus, completing the access in a single cycle. If the data is not mapped into the tag
memory, a cache miss occurs and the processor core initiates a 16-byte line-sized fetch. The cache module
相关PDF资料 |
PDF描述 |
|---|---|
| MCF5472ZP200 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| MC9S08RD8CFJ | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
| MC68L11E0PB2 | 8-BIT, 2 MHz, MICROCONTROLLER, PQFP52 |
| MC68L11E1FN2 | 8-BIT, 2 MHz, MICROCONTROLLER, PQCC52 |
| MC68L11E1FU2 | 8-BIT, 2 MHz, MICROCONTROLLER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MCF5233CVM150J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
| MCF5234 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Microprocessor Hardware Specification |
| MCF5234256MAPBGA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Microprocessor Hardware Specification |
| MCF5234CVM100 | 功能描述:微处理器 - MPU MCF5234 V2CORE 64KSRAM RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MCF5234CVM100J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。