参数资料
型号: MCF5233CVM150
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
封装: MAPBGA-256
文件页数: 4/76页
文件大小: 2665K
代理商: MCF5233CVM150
12
MCF523x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
includes a 16-byte line fill buffer used as temporary storage during miss processing. For all data cache
configurations, the memory operates in write-through mode and all operand writes generate an external bus
cycle.
1.3.7.2
SRAM
The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access
in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte
address space. The memory is ideal for storing critical code or data structures, for use as the system stack,
or for storing FEC data buffers. Because the SRAM module is physically connected to the processor’s
high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from
the debug module.
The SRAM module is also accessible by the DMA and FEC non-core bus masters. The dual-ported nature
of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor
and a DMA device operate in alternate regions of the SRAM to maximize system performance. As an
example, system performance can be increased significantly if Ethernet packets are moved from the FEC
into the SRAM (rather than external memory) prior to any processing.
1.3.8
Fast Ethernet Controller (FEC)
The MCF523x’s integrated Fast Ethernet Controller (FEC) performs the full set of IEEE 802.3/Ethernet
CSMA/CD media access control and channel interface functions. The FEC supports connection and
functionality for the 10/100 Mbps 802.3 media independent interface (MII). It requires an external
transceiver (PHY) to complete the interface to the media.
1.3.9
FlexCAN
There are up to 2 FlexCAN modules on the MCF523x (refer to Table 1). The FlexCAN module is a
communication controller implementing the 2.0B CAN protocol. The CAN protocol is commonly used as
an industrial control serial data bus, meeting the specific requirements of real-time processing, reliable
operation in a harsh EMI environment, cost-effectiveness, and required bandwidth. FlexCAN contains 16
message buffers.
1.3.10 UARTs
The MCF523x contains three full-duplex UARTs that function independently. The three UARTs can be
clocked by the system bus clock, eliminating the need for an externally supplied clock. They can use DMA
requests on transmit-ready and recieve-ready as well as interrput requests for servicing. Flow control is only
available on two of the UARTs.
1.3.11 I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. This bus is suitable for applications requiring occasional
communications over a short distance between many devices.
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