
18-10
MCF5249UM
MOTOROLA
Programming Model
18.5.4
I2C STATUS REGISTERS (MBSR)
This status register is read-only with the exception of bit 1 (IIF) and bit 4 (IAL), which can be cleared by
software. All bits are cleared on reset except bit 7 (ICF) and bit 0 (RXAK), which are set (=1) at reset.
Table 18-9 MBSR Register
BITS
7
6
5
4
3
2
1
0
FIELD
ICF
IAAS
IBB
IAL
-
SRW
IIF
RXAK
RESET
1
00
1
R/W
READ/WRITE SUPERVISOR OR USER MODE
ADDR
MBAR+ $28C (MBSR)
MBAR2+ $44C (MBSR2)
Table 18-10 MBSR Bit Descriptions
BIT NAME
DESCRIPTION
ICF
While one byte of data is being transferred, the Data Transferring Bit bit is cleared. It is set by
the falling edge of the 9th clock of a byte transfer.
1 = Transfer complete
0 = Transfer in progress
IAAS
When its own specific address (I2C Address Register) is matched with the calling address,
the Addressed as a Slave Bit is set. The CPU is interrupted provided the IIEN is set. Next,
the CPU must check the SRW bit and set its TX/RX mode accordingly. Writing to the I2C
Control Register clears this bit.
1 = Addressed as a slave
0 = Not addressed
IBB
The Bus Busy Bit indicates the status of the bus. When a START signal is detected, the IBB
is set. If a STOP signal is detected, it is cleared.
1 = Bus is busy
0 = Bus is idle
IAL
Hardware sets the Arbitration Lost bit (IAL) when the arbitration procedure is lost. Arbitration
is lost in the following circumstances:
SDA sampled as low when the master drives a high during an address or data-transmit
cycle.
SDA sampled as a low when the master drives a high during the acknowledge bit of a
data-receive cycle.
A start cycle is attempted when the bus is busy.
A repeated start cycle is requested in slave mode.
A stop condition is detected when the master did not request it.
This bit must be cleared by software by writing a zero to it.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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