
Real-Time Debug Support
MOTOROLA
Debug Support
19-31
19.4.2.3
Program Counter Breakpoint Register (PBR, PBMR)
The PC breakpoint registers (PBR and PBMR) define a region in the code address space of the processor
that can be used as part of the trigger. The PBR value is masked by the PBMR value, allowing only those
bits in PBR that have a corresponding zero in PBMR to be compared with the processor’s program counter
register, as defined in the
TDR. The PBR is accessible in supervisor mode as debug control register $8
using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands.
The PBMR is accessible in supervisor mode as debug control register $9 using the WDEBUG instruction
and through the BDM port using the WDMREG command.
TM [2:0]
The transfer modifier field is compared with the transfer modifier signals of the processor’s
local bus. The signals provide supplemental information for each transfer type.
The encoding for normal processor transfers (TT = 0) is:
000 = Explicit Cache Line Push
001 = User Data Access
010 = User Code Access
011 = Reserved
100 = Reserved
101 = Supervisor Data Access
110 = Supervisor Code Access
111 = Reserved
The encoding for emulator mode transfers (TT = 10) is:
0xx = Reserved
100 = Reserved
101 = Emulator Mode Data Access
110 = Emulator Mode Code Access
111 = Reserved
The encoding for acknowledge/CPU space transfers (TT = 11) is:
000 = CPU Space Access
001 = Interrupt Acknowledge Level 1
010 = Interrupt Acknowledge Level 2
011 = Interrupt Acknowledge Level 3
100 = Interrupt Acknowledge Level 4
101 = Interrupt Acknowledge Level 5
110 = Interrupt Acknowledge Level 6
111 = Interrupt Acknowledge Level 7
These bits also define the TM encoding for BDM memory commands (For backward
compatibility).
Table 19-25 Address Attribute Trigger Bit Descriptions (Continued)
BIT NAME
DESCRIPTION
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.